[PATCH] D26648: Clarify semantic of reserved registers.

[Matthias Braun via llvm-commits]

MatzeB added a reviewer: sdardis.
MatzeB added a comment.

These new rules break existing use in Mips :-(

Mips has 32bit floatregs F0-F31, each pair forms a double reg (F0+https://reviews.llvm.org/F1=D0, https://reviews.llvm.org/F2+https://reviews.llvm.org/F3=https://reviews.llvm.org/D1, ...). There is an option in the mips backend that aims at disabling the odd F registers, so 32bit float values only end up in F0, https://reviews.llvm.org/F2, https://reviews.llvm.org/F4, ... In this case it is actually expected that the register allocator still assigns the D0-D15 as usual even though the would indirectly use https://reviews.llvm.org/F1,https://reviews.llvm.org/F3,...

Is there another way to handle this in the mips target?


Repository:
  rL LLVM

https://reviews.llvm.org/D26648