[PATCH] D26620: [X86][FastISel] Fix lowering of overflow result on AVX512 targets

[Zvi Rackover via llvm-commits]

zvi created this revision.
zvi added reviewers: mkuper, igorb, craig.topper, guyblank.
zvi added a subscriber: llvm-commits.
zvi set the repository for this revision to rL LLVM.

Fix a case where the overflow value of type i1, which is legal on AVX512, was assigned to a VK1 register class.
We always want this value to be assigned to a GPR since the overflow return value is lowered to a SETO instruction.

Fixes pr30981.


Repository:
  rL LLVM

https://reviews.llvm.org/D26620

Files:
  lib/Target/X86/X86FastISel.cpp
  test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll


Index: test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
===================================================================
--- test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
+++ test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
@@ -10,14 +10,14 @@
 
 define fastcc i32 @test() nounwind {
 entry:
-; CHECK-LABEL: _test:
-; CHECK:      ## BB#0:
-; CHECK-NEXT: movl    $1, %eax
-; CHECK-NEXT: addl    $0, %eax
-; CHECK-NEXT: seto    %k0
-; CHECK-NEXT: movl    %eax, -4(%rsp)          ## 4-byte Spill
-; CHECK-NEXT: kmovw   %k0, -6(%rsp)           ## 2-byte Spill
-; CHECK-NEXT: jo      LBB0_2
+; CHECK-LABEL: test:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    addl $0, %eax
+; CHECK-NEXT:    seto %cl
+; CHECK-NEXT:    movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
+; CHECK-NEXT:    movb %cl, -{{[0-9]+}}(%rsp) ## 1-byte Spill
+; CHECK-NEXT:    jo LBB0_2
 	%tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
 	%tmp2 = extractvalue %0 %tmp1, 1
 	br i1 %tmp2, label %.backedge, label %BB3
Index: lib/Target/X86/X86FastISel.cpp
===================================================================
--- lib/Target/X86/X86FastISel.cpp
+++ lib/Target/X86/X86FastISel.cpp
@@ -2769,7 +2769,9 @@
     const Function *Callee = II->getCalledFunction();
     auto *Ty = cast<StructType>(Callee->getReturnType());
     Type *RetTy = Ty->getTypeAtIndex(0U);
-    Type *CondTy = Ty->getTypeAtIndex(1);
+    assert(Ty->getTypeAtIndex(1)->isIntegerTy() &&
+           Ty->getTypeAtIndex(1)->getScalarSizeInBits() == 1 &&
+           "Overflow value expected to be an i1");
 
     MVT VT;
     if (!isTypeLegal(RetTy, VT))
@@ -2879,7 +2881,7 @@
     if (!ResultReg)
       return false;
 
-    unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
+    unsigned ResultReg2 = createResultReg(&X86::GR8RegClass);
     assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
             ResultReg2);


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