[PATCH] D26396: [AArch64] Enable merging of adjacent zero stores for all subtargets.

[Chad Rosier via llvm-commits]

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In https://reviews.llvm.org/D26396#592260, @MatzeB wrote:

> LGTM, nitpick below.
>
> BTW: I tried to find some discussion of why we have this load/store combining feature in the AArch64 target (don't we already have that in GVN and other places in the middleend?) but couldn't find any reviews or discussions that would motivate it.


Thanks for the review, Matthias.  I'll follow up on your question with @junbuml as he was the original author of this optimization.  I thought we did a similar form of combing at isel lowering, but I may be mistaken.



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Comment at: test/CodeGen/AArch64/arm64-narrow-st-merge.ll:1-8
+; RUN: llc < %s -mtriple aarch64--none-eabi -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=kryo -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cyclone -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=exynos-m1 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=exynos-m2 -verify-machineinstrs | FileCheck %s
----------------
MatzeB wrote:
> I don't see the benefits of testing this for every CPU in the AArch64 target. Maybe 1 single RUN: is enough here?
Sure.


https://reviews.llvm.org/D26396