[PATCH] D26120: [Cortex-M0] Atomic lowering

[Eli Friedman via llvm-commits]

efriedma added a comment.

  bool ARMSubtarget::enableAtomicExpand() const {
    return hasAnyDataBarrier();
  }



  TargetLowering::AtomicExpansionKind
  ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
    unsigned Size = AI->getType()->getPrimitiveSizeInBits();
    return ((!isThumb() || hasV8MBaselineOps()) && Size <= (Subtarget->isMClass() ? 32U : 64U))
               ? AtomicExpansionKind::LLSC
               : AtomicExpansionKind::None;
  }

Is this not sufficient for some reason?


Repository:
  rL LLVM

https://reviews.llvm.org/D26120