[PATCH] D26120: [Cortex-M0] Atomic lowering

[Weiming Zhao via llvm-commits]

weimingz added a comment.

Hi Eli,

I think the problem is the feature for armv6m is not well defined.
ARMv6m is mostly Thumb1, but it also supports 5 32-bit instrs: DL, DMB, DSB. ISM. MRS, MSR

In ARM.td, FeatureDB has already been defined for Armv6m.
However,  when existing code actually checks for availability of atomic feature (fence + ldrex/strex), if the target is Thumb but not supports ARMv8mBaseline, then it assumes no such feature.

For example: in  ARMISelLowering.cpp::1043

  if (Subtarget->hasAnyDataBarrier() &&
      (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())


Repository:
  rL LLVM

https://reviews.llvm.org/D26120