[llvm] r283831 - [AArch64][InstructionSelector] Teach the selector how to handle vector OR.

Quentin Colombet via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 10 17:21:12 PDT 2016


Author: qcolombet
Date: Mon Oct 10 19:21:11 2016
New Revision: 283831

URL: http://llvm.org/viewvc/llvm-project?rev=283831&view=rev
Log:
[AArch64][InstructionSelector] Teach the selector how to handle vector OR.

This only adds the support for 64-bit vector OR. Adding more sizes is
not difficult, but it requires a bigger refactoring because ORs work on
any size, not necessarly the ones that match the width of the register
width. Right now, this is not expressed in the legalization, so don't
bother pushing the refactoring yet.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=283831&r1=283830&r2=283831&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Oct 10 19:21:11 2016
@@ -175,6 +175,8 @@ static unsigned selectBinaryOp(unsigned
         return AArch64::FMULDrr;
       case TargetOpcode::G_FDIV:
         return AArch64::FDIVDrr;
+      case TargetOpcode::G_OR:
+        return AArch64::ORRv8i8;
       default:
         return GenericOpc;
       }

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=283831&r1=283830&r2=283831&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Mon Oct 10 19:21:11 2016
@@ -15,6 +15,7 @@
 
   define void @or_s32_gpr() { ret void }
   define void @or_s64_gpr() { ret void }
+  define void @or_v2s32_fpr() { ret void }
 
   define void @xor_s32_gpr() { ret void }
   define void @xor_s64_gpr() { ret void }
@@ -255,6 +256,37 @@ body:             |
 ...
 
 ---
+# 64-bit G_OR on vector registers.
+# CHECK-LABEL: name: or_v2s32_fpr
+name:            or_v2s32_fpr
+legalized:       true
+regBankSelected: true
+#
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: fpr64 }
+# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 2, class: fpr64 }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = COPY %d1
+# The actual OR does not matter as long as it is operating
+# on 64-bit width vector.
+# CHECK:    %2 = ORRv8i8 %0, %1
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+      %0(<2 x s32>) = COPY %d0
+      %1(<2 x s32>) = COPY %d1
+      %2(<2 x s32>) = G_OR %0, %1
+...
+
+---
 # Same as add_s32_gpr, for G_XOR operations.
 # CHECK-LABEL: name: xor_s32_gpr
 name:            xor_s32_gpr




More information about the llvm-commits mailing list