[llvm] r283542 - [ARM]: Add Cortex-R52 target to LLVM
Javed Absar via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 7 13:27:49 PDT 2016
Hi :
I submitted new patch https://reviews.llvm.org/rL283551 to address this issue.
Best Regards
Javed
From: Galina Kistanova [mailto:gkistanova at gmail.com]
Sent: 07 October 2016 19:42
To: Javed Absar
Cc: Artur Pilipenko via llvm-commits
Subject: Re: [llvm] r283542 - [ARM]: Add Cortex-R52 target to LLVM
Hello,
It looks like this revision broke one of builders:
http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/692
Please have a look at this?
Thanks
Galina
On Fri, Oct 7, 2016 at 5:06 AM, Javed Absar via llvm-commits <llvm-commits at lists.llvm.org<mailto:llvm-commits at lists.llvm.org>> wrote:
Author: javed.absar
Date: Fri Oct 7 07:06:40 2016
New Revision: 283542
URL: http://llvm.org/viewvc/llvm-project?rev=283542&view=rev
Log:
[ARM]: Add Cortex-R52 target to LLVM
This patch adds Cortex-R52, the new ARM real-time processor, to LLVM.
Cortex-R52 implements the ARMv8-R architecture.
Modified:
llvm/trunk/include/llvm/ADT/Triple.h
llvm/trunk/include/llvm/Support/ARMBuildAttributes.h
llvm/trunk/include/llvm/Support/ARMTargetParser.def
llvm/trunk/lib/Support/TargetParser.cpp
llvm/trunk/lib/Support/Triple.cpp
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/test/CodeGen/ARM/build-attributes.ll
llvm/trunk/unittests/Support/TargetParserTest.cpp
Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Fri Oct 7 07:06:40 2016
@@ -99,6 +99,7 @@ public:
ARMSubArch_v8_2a,
ARMSubArch_v8_1a,
ARMSubArch_v8,
+ ARMSubArch_v8r,
ARMSubArch_v8m_baseline,
ARMSubArch_v8m_mainline,
ARMSubArch_v7,
Modified: llvm/trunk/include/llvm/Support/ARMBuildAttributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMBuildAttributes.h?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMBuildAttributes.h (original)
+++ llvm/trunk/include/llvm/Support/ARMBuildAttributes.h Fri Oct 7 07:06:40 2016
@@ -108,6 +108,7 @@ enum CPUArch {
v6S_M = 12, // v6_M with the System extensions
v7E_M = 13, // v7_M with DSP extensions
v8_A = 14, // v8_A AArch32
+ v8_R = 15, // e.g. Cortex R52
v8_M_Base= 16, // v8_M_Base AArch32
v8_M_Main= 17, // v8_M_Main AArch32
};
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Fri Oct 7 07:06:40 2016
@@ -94,6 +94,10 @@ ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
+ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
+ FK_NEON_FP_ARMV8,
+ (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |
+ ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base",
ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIV)
ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main",
@@ -220,6 +224,7 @@ ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
+ARM_CPU_NAME("cortex-r52", AK_ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE)
ARM_CPU_NAME("sc300", AK_ARMV7M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
Modified: llvm/trunk/lib/Support/TargetParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/lib/Support/TargetParser.cpp (original)
+++ llvm/trunk/lib/Support/TargetParser.cpp Fri Oct 7 07:06:40 2016
@@ -578,6 +578,7 @@ static StringRef getArchSynonym(StringRe
.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
.Case("v8.1a", "v8.1-a")
.Case("v8.2a", "v8.2-a")
+ .Case("v8r", "v8-r")
.Case("v8m.base", "v8-m.base")
.Case("v8m.main", "v8-m.main")
.Default(Arch);
@@ -721,6 +722,7 @@ unsigned llvm::ARM::parseArchProfile(Str
case ARM::AK_ARMV8MBaseline:
return ARM::PK_M;
case ARM::AK_ARMV7R:
+ case ARM::AK_ARMV8R:
return ARM::PK_R;
case ARM::AK_ARMV7A:
case ARM::AK_ARMV7K:
@@ -768,6 +770,7 @@ unsigned llvm::ARM::parseArchVersion(Str
case ARM::AK_ARMV8A:
case ARM::AK_ARMV8_1A:
case ARM::AK_ARMV8_2A:
+ case ARM::AK_ARMV8R:
case ARM::AK_ARMV8MBaseline:
case ARM::AK_ARMV8MMainline:
return 8;
Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Fri Oct 7 07:06:40 2016
@@ -550,6 +550,8 @@ static Triple::SubArchType parseSubArch(
return Triple::ARMSubArch_v8_1a;
case ARM::AK_ARMV8_2A:
return Triple::ARMSubArch_v8_2a;
+ case ARM::AK_ARMV8R:
+ return Triple::ARMSubArch_v8r;
case ARM::AK_ARMV8MBaseline:
return Triple::ARMSubArch_v8m_baseline;
case ARM::AK_ARMV8MMainline:
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Fri Oct 7 07:06:40 2016
@@ -353,6 +353,8 @@ def ProcR5 : SubtargetFeature<"r5",
"Cortex-R5 ARM processors", []>;
def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
"Cortex-R7 ARM processors", []>;
+def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
+ "Cortex-R52 ARM processors", []>;
def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
"Cortex-M3 ARM processors", []>;
@@ -474,6 +476,19 @@ def ARMv82a : Architecture<"armv8.2-a"
FeatureCRC,
FeatureRAS]>;
+def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
+ FeatureRClass,
+ FeatureDB,
+ FeatureHWDiv,
+ FeatureHWDivARM,
+ FeatureT2XtPk,
+ FeatureDSP,
+ FeatureCRC,
+ FeatureMP,
+ FeatureVirtualization,
+ FeatureFPARMv8,
+ FeatureNEON]>;
+
def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
[HasV8MBaselineOps,
FeatureNoARM,
@@ -804,6 +819,8 @@ def : ProcNoItin<"exynos-m2",
FeatureCrypto,
FeatureCRC]>;
+def : ProcNoItin<"cortex-r52", [ARMv8r, ProcR52]>;
+
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Oct 7 07:06:40 2016
@@ -605,9 +605,11 @@ static ARMBuildAttrs::CPUArch getArchFor
if (CPU == "xscale")
return ARMBuildAttrs::v5TEJ;
- if (Subtarget->hasV8Ops())
+ if (Subtarget->hasV8Ops()) {
+ if (Subtarget->isRClass())
+ return ARMBuildAttrs::v8_R;
return ARMBuildAttrs::v8_A;
- else if (Subtarget->hasV8MMainlineOps())
+ } else if (Subtarget->hasV8MMainlineOps())
return ARMBuildAttrs::v8_M_Main;
else if (Subtarget->hasV7Ops()) {
if (Subtarget->isMClass() && Subtarget->hasDSP())
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Oct 7 07:06:40 2016
@@ -43,7 +43,7 @@ class ARMSubtarget : public ARMGenSubtar
protected:
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
- CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,
+ CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3,
CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
Krait, Swift, ExynosM1
};
@@ -53,7 +53,8 @@ protected:
enum ARMArchEnum {
ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
- ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline
+ ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline,
+ ARMv8r
};
public:
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Fri Oct 7 07:06:40 2016
@@ -200,6 +200,11 @@
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; ARMv8-R
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-vfp2,-fp16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NOFPU
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-neon,+fp-only-sp,+d16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-SP
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NEON
+
; XSCALE: .eabi_attribute 6, 5
; XSCALE: .eabi_attribute 8, 1
; XSCALE: .eabi_attribute 9, 1
@@ -1549,6 +1554,35 @@
; PCS-R9-USE: .eabi_attribute 14, 0
; PCS-R9-RESERVE: .eabi_attribute 14, 3
+; ARMv8R: .eabi_attribute 67, "2.09" @ Tag_conformance
+; ARMv8R: .eabi_attribute 6, 15 @ Tag_CPU_arch
+; ARMv8R: .eabi_attribute 7, 82 @ Tag_CPU_arch_profile
+; ARMv8R: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
+; ARMv8R: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
+; ARMv8R-NOFPU-NOT: .fpu
+; ARMv8R-NOFPU-NOT: .eabi_attribute 12
+; ARMv8R-SP: .fpu fpv5-sp-d16
+; ARMv8R-SP-NOT: .eabi_attribute 12
+; ARMv8R-NEON: .fpu neon-fp-armv8
+; ARMv8R-NEON: .eabi_attribute 12, 3 @ Tag_Advanced_SIMD_arch
+; ARMv8R: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use
+; ARMv8R: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
+; ARMv8R: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
+; ARMv8R: .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
+; ARMv8R: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+; ARMv8R: .eabi_attribute 24, 1 @ Tag_ABI_align_needed
+; ARMv8R: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved
+; ARMv8R-NOFPU-NOT: .eabi_attribute 27
+; ARMv8R-SP: .eabi_attribute 27, 1 @ Tag_ABI_HardFP_use
+; ARMv8R-NEON-NOT: .eabi_attribute 27
+; ARMv8R-NOFPU-NOT: .eabi_attribute 36
+; ARMv8R-SP: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
+; ARMv8R-NEON: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
+; ARMv8R: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format
+; ARMv8R: .eabi_attribute 42, 1 @ Tag_MPextension_use
+; ARMv8R: .eabi_attribute 14, 0 @ Tag_ABI_PCS_R9_use
+; ARMv8R: .eabi_attribute 68, 2 @ Tag_Virtualization_use
+
define i32 @f(i64 %z) {
ret i32 0
}
Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=283542&r1=283541&r2=283542&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp Fri Oct 7 07:06:40 2016
@@ -318,7 +318,7 @@ TEST(TargetParserTest, ARMparseCPUArch)
"cortex-m3", "cortex-m4", "cortex-m7", "cortex-a32",
"cortex-a35", "cortex-a53", "cortex-a57", "cortex-a72",
"cortex-a73", "cyclone", "exynos-m1", "exynos-m2",
- "iwmmxt", "xscale", "swift"};
+ "iwmmxt", "xscale", "swift", "cortex-r52"};
for (const auto &ARMCPUName : kARMCPUNames) {
if (contains(CPU, ARMCPUName.Name))
@@ -335,7 +335,7 @@ TEST(TargetParserTest, ARMparseArchEndia
"v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a",
"v7", "v7a", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m",
"v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v8.1-a",
- "v8.1a", "v8.2-a", "v8.2a"};
+ "v8.1a", "v8.2-a", "v8.2a", "v8-r"};
for (unsigned i = 0; i < array_lengthof(Arch); i++) {
std::string arm_1 = "armeb" + (std::string)(Arch[i]);
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