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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi :<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span style="color:#1F497D">I submitted new patch </span>
<a href="https://reviews.llvm.org/rL283551">https://reviews.llvm.org/rL283551</a> to address this issue.
<o:p></o:p></p>
<p class="MsoPlainText">Best Regards <o:p></o:p></p>
<p class="MsoPlainText">Javed <o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Galina Kistanova [mailto:gkistanova@gmail.com]
<br>
<b>Sent:</b> 07 October 2016 19:42<br>
<b>To:</b> Javed Absar<br>
<b>Cc:</b> Artur Pilipenko via llvm-commits<br>
<b>Subject:</b> Re: [llvm] r283542 - [ARM]: Add Cortex-R52 target to LLVM<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Hello,<br>
<br>
It looks like this revision broke one of builders:<br>
<a href="http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/692">http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/692</a><br>
<br>
Please have a look at this?<br>
<br>
Thanks<br>
<br>
Galina<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">On Fri, Oct 7, 2016 at 5:06 AM, Javed Absar via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal">Author: javed.absar<br>
Date: Fri Oct 7 07:06:40 2016<br>
New Revision: 283542<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=283542&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=283542&view=rev</a><br>
Log:<br>
[ARM]: Add Cortex-R52 target to LLVM<br>
<br>
This patch adds Cortex-R52, the new ARM real-time processor, to LLVM.<br>
Cortex-R52 implements the ARMv8-R architecture.<br>
<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/ADT/Triple.h<br>
llvm/trunk/include/llvm/Support/ARMBuildAttributes.h<br>
llvm/trunk/include/llvm/Support/ARMTargetParser.def<br>
llvm/trunk/lib/Support/TargetParser.cpp<br>
llvm/trunk/lib/Support/Triple.cpp<br>
llvm/trunk/lib/Target/ARM/ARM.td<br>
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.h<br>
llvm/trunk/test/CodeGen/ARM/build-attributes.ll<br>
llvm/trunk/unittests/Support/TargetParserTest.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/ADT/Triple.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/ADT/Triple.h (original)<br>
+++ llvm/trunk/include/llvm/ADT/Triple.h Fri Oct 7 07:06:40 2016<br>
@@ -99,6 +99,7 @@ public:<br>
ARMSubArch_v8_2a,<br>
ARMSubArch_v8_1a,<br>
ARMSubArch_v8,<br>
+ ARMSubArch_v8r,<br>
ARMSubArch_v8m_baseline,<br>
ARMSubArch_v8m_mainline,<br>
ARMSubArch_v7,<br>
<br>
Modified: llvm/trunk/include/llvm/Support/ARMBuildAttributes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMBuildAttributes.h?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMBuildAttributes.h?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/ARMBuildAttributes.h (original)<br>
+++ llvm/trunk/include/llvm/Support/ARMBuildAttributes.h Fri Oct 7 07:06:40 2016<br>
@@ -108,6 +108,7 @@ enum CPUArch {<br>
v6S_M = 12, // v6_M with the System extensions<br>
v7E_M = 13, // v7_M with DSP extensions<br>
v8_A = 14, // v8_A AArch32<br>
+ v8_R = 15, // e.g. Cortex R52<br>
v8_M_Base= 16, // v8_M_Base AArch32<br>
v8_M_Main= 17, // v8_M_Main AArch32<br>
};<br>
<br>
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)<br>
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Fri Oct 7 07:06:40 2016<br>
@@ -94,6 +94,10 @@ ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-<br>
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,<br>
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |<br>
ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))<br>
+ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,<br>
+ FK_NEON_FP_ARMV8,<br>
+ (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |<br>
+ ARM::AEK_DSP | ARM::AEK_CRC))<br>
ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base",<br>
ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIV)<br>
ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main",<br>
@@ -220,6 +224,7 @@ ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_<br>
(ARM::AEK_MP | ARM::AEK_HWDIVARM))<br>
ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false,<br>
(ARM::AEK_MP | ARM::AEK_HWDIVARM))<br>
+ARM_CPU_NAME("cortex-r52", AK_ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE)<br>
ARM_CPU_NAME("sc300", AK_ARMV7M, FK_NONE, false, ARM::AEK_NONE)<br>
ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true, ARM::AEK_NONE)<br>
ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)<br>
<br>
Modified: llvm/trunk/lib/Support/TargetParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/TargetParser.cpp (original)<br>
+++ llvm/trunk/lib/Support/TargetParser.cpp Fri Oct 7 07:06:40 2016<br>
@@ -578,6 +578,7 @@ static StringRef getArchSynonym(StringRe<br>
.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")<br>
.Case("v8.1a", "v8.1-a")<br>
.Case("v8.2a", "v8.2-a")<br>
+ .Case("v8r", "v8-r")<br>
.Case("v8m.base", "v8-m.base")<br>
.Case("v8m.main", "v8-m.main")<br>
.Default(Arch);<br>
@@ -721,6 +722,7 @@ unsigned llvm::ARM::parseArchProfile(Str<br>
case ARM::AK_ARMV8MBaseline:<br>
return ARM::PK_M;<br>
case ARM::AK_ARMV7R:<br>
+ case ARM::AK_ARMV8R:<br>
return ARM::PK_R;<br>
case ARM::AK_ARMV7A:<br>
case ARM::AK_ARMV7K:<br>
@@ -768,6 +770,7 @@ unsigned llvm::ARM::parseArchVersion(Str<br>
case ARM::AK_ARMV8A:<br>
case ARM::AK_ARMV8_1A:<br>
case ARM::AK_ARMV8_2A:<br>
+ case ARM::AK_ARMV8R:<br>
case ARM::AK_ARMV8MBaseline:<br>
case ARM::AK_ARMV8MMainline:<br>
return 8;<br>
<br>
Modified: llvm/trunk/lib/Support/Triple.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/Triple.cpp (original)<br>
+++ llvm/trunk/lib/Support/Triple.cpp Fri Oct 7 07:06:40 2016<br>
@@ -550,6 +550,8 @@ static Triple::SubArchType parseSubArch(<br>
return Triple::ARMSubArch_v8_1a;<br>
case ARM::AK_ARMV8_2A:<br>
return Triple::ARMSubArch_v8_2a;<br>
+ case ARM::AK_ARMV8R:<br>
+ return Triple::ARMSubArch_v8r;<br>
case ARM::AK_ARMV8MBaseline:<br>
return Triple::ARMSubArch_v8m_baseline;<br>
case ARM::AK_ARMV8MMainline:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARM.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARM.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARM.td Fri Oct 7 07:06:40 2016<br>
@@ -353,6 +353,8 @@ def ProcR5 : SubtargetFeature<"r5",<br>
"Cortex-R5 ARM processors", []>;<br>
def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",<br>
"Cortex-R7 ARM processors", []>;<br>
+def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",<br>
+ "Cortex-R52 ARM processors", []>;<br>
<br>
def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",<br>
"Cortex-M3 ARM processors", []>;<br>
@@ -474,6 +476,19 @@ def ARMv82a : Architecture<"armv8.2-a"<br>
FeatureCRC,<br>
FeatureRAS]>;<br>
<br>
+def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,<br>
+ FeatureRClass,<br>
+ FeatureDB,<br>
+ FeatureHWDiv,<br>
+ FeatureHWDivARM,<br>
+ FeatureT2XtPk,<br>
+ FeatureDSP,<br>
+ FeatureCRC,<br>
+ FeatureMP,<br>
+ FeatureVirtualization,<br>
+ FeatureFPARMv8,<br>
+ FeatureNEON]>;<br>
+<br>
def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",<br>
[HasV8MBaselineOps,<br>
FeatureNoARM,<br>
@@ -804,6 +819,8 @@ def : ProcNoItin<"exynos-m2",<br>
FeatureCrypto,<br>
FeatureCRC]>;<br>
<br>
+def : ProcNoItin<"cortex-r52", [ARMv8r, ProcR52]>;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// Register File Description<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Oct 7 07:06:40 2016<br>
@@ -605,9 +605,11 @@ static ARMBuildAttrs::CPUArch getArchFor<br>
if (CPU == "xscale")<br>
return ARMBuildAttrs::v5TEJ;<br>
<br>
- if (Subtarget->hasV8Ops())<br>
+ if (Subtarget->hasV8Ops()) {<br>
+ if (Subtarget->isRClass())<br>
+ return ARMBuildAttrs::v8_R;<br>
return ARMBuildAttrs::v8_A;<br>
- else if (Subtarget->hasV8MMainlineOps())<br>
+ } else if (Subtarget->hasV8MMainlineOps())<br>
return ARMBuildAttrs::v8_M_Main;<br>
else if (Subtarget->hasV7Ops()) {<br>
if (Subtarget->isMClass() && Subtarget->hasDSP())<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Oct 7 07:06:40 2016<br>
@@ -43,7 +43,7 @@ class ARMSubtarget : public ARMGenSubtar<br>
protected:<br>
enum ARMProcFamilyEnum {<br>
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,<br>
- CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,<br>
+ CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3,<br>
CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,<br>
Krait, Swift, ExynosM1<br>
};<br>
@@ -53,7 +53,8 @@ protected:<br>
enum ARMArchEnum {<br>
ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,<br>
ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,<br>
- ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline<br>
+ ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline,<br>
+ ARMv8r<br>
};<br>
<br>
public:<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Fri Oct 7 07:06:40 2016<br>
@@ -200,6 +200,11 @@<br>
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=NO-STRICT-ALIGN<br>
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN<br>
<br>
+; ARMv8-R<br>
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-vfp2,-fp16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NOFPU<br>
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-neon,+fp-only-sp,+d16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-SP<br>
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NEON<br>
+<br>
; XSCALE: .eabi_attribute 6, 5<br>
; XSCALE: .eabi_attribute 8, 1<br>
; XSCALE: .eabi_attribute 9, 1<br>
@@ -1549,6 +1554,35 @@<br>
; PCS-R9-USE: .eabi_attribute 14, 0<br>
; PCS-R9-RESERVE: .eabi_attribute 14, 3<br>
<br>
+; ARMv8R: .eabi_attribute 67, "2.09" @ Tag_conformance<br>
+; ARMv8R: .eabi_attribute 6, 15 @ Tag_CPU_arch<br>
+; ARMv8R: .eabi_attribute 7, 82 @ Tag_CPU_arch_profile<br>
+; ARMv8R: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use<br>
+; ARMv8R: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use<br>
+; ARMv8R-NOFPU-NOT: .fpu<br>
+; ARMv8R-NOFPU-NOT: .eabi_attribute 12<br>
+; ARMv8R-SP: .fpu fpv5-sp-d16<br>
+; ARMv8R-SP-NOT: .eabi_attribute 12<br>
+; ARMv8R-NEON: .fpu neon-fp-armv8<br>
+; ARMv8R-NEON: .eabi_attribute 12, 3 @ Tag_Advanced_SIMD_arch<br>
+; ARMv8R: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use<br>
+; ARMv8R: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal<br>
+; ARMv8R: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions<br>
+; ARMv8R: .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model<br>
+; ARMv8R: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access<br>
+; ARMv8R: .eabi_attribute 24, 1 @ Tag_ABI_align_needed<br>
+; ARMv8R: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved<br>
+; ARMv8R-NOFPU-NOT: .eabi_attribute 27<br>
+; ARMv8R-SP: .eabi_attribute 27, 1 @ Tag_ABI_HardFP_use<br>
+; ARMv8R-NEON-NOT: .eabi_attribute 27<br>
+; ARMv8R-NOFPU-NOT: .eabi_attribute 36<br>
+; ARMv8R-SP: .eabi_attribute 36, 1 @ Tag_FP_HP_extension<br>
+; ARMv8R-NEON: .eabi_attribute 36, 1 @ Tag_FP_HP_extension<br>
+; ARMv8R: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format<br>
+; ARMv8R: .eabi_attribute 42, 1 @ Tag_MPextension_use<br>
+; ARMv8R: .eabi_attribute 14, 0 @ Tag_ABI_PCS_R9_use<br>
+; ARMv8R: .eabi_attribute 68, 2 @ Tag_Virtualization_use<br>
+<br>
define i32 @f(i64 %z) {<br>
ret i32 0<br>
}<br>
<br>
Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=283542&r1=283541&r2=283542&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=283542&r1=283541&r2=283542&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)<br>
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp Fri Oct 7 07:06:40 2016<br>
@@ -318,7 +318,7 @@ TEST(TargetParserTest, ARMparseCPUArch)<br>
"cortex-m3", "cortex-m4", "cortex-m7", "cortex-a32",<br>
"cortex-a35", "cortex-a53", "cortex-a57", "cortex-a72",<br>
"cortex-a73", "cyclone", "exynos-m1", "exynos-m2",<br>
- "iwmmxt", "xscale", "swift"};<br>
+ "iwmmxt", "xscale", "swift", "cortex-r52"};<br>
<br>
for (const auto &ARMCPUName : kARMCPUNames) {<br>
if (contains(CPU, ARMCPUName.Name))<br>
@@ -335,7 +335,7 @@ TEST(TargetParserTest, ARMparseArchEndia<br>
"v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a",<br>
"v7", "v7a", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m",<br>
"v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v8.1-a",<br>
- "v8.1a", "v8.2-a", "v8.2a"};<br>
+ "v8.1a", "v8.2-a", "v8.2a", "v8-r"};<br>
<br>
for (unsigned i = 0; i < array_lengthof(Arch); i++) {<br>
std::string arm_1 = "armeb" + (std::string)(Arch[i]);<br>
<br>
<br>
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