[PATCH] D24459: [SelectionDAGBuilder] Support llvm.flt.rounds on targets where i32 is not legal
Edward Jones via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 7 06:14:24 PDT 2016
edward-jones updated this revision to Diff 73923.
edward-jones added a comment.
Added a comment, and re-add the msp430 test from the first patch.
If this is acceptable, is it okay for someone to commit this on my behalf.
https://reviews.llvm.org/D24459
Files:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeTypes.h
test/CodeGen/MSP430/flt_rounds.ll
Index: test/CodeGen/MSP430/flt_rounds.ll
===================================================================
--- /dev/null
+++ test/CodeGen/MSP430/flt_rounds.ll
@@ -0,0 +1,10 @@
+; RUN: llc -verify-machineinstrs < %s -march=msp430
+
+define i16 @foo() {
+entry:
+ %0 = call i32 @llvm.flt.rounds()
+ %1 = trunc i32 %0 to i16
+ ret i16 %1
+}
+
+declare i32 @llvm.flt.rounds() nounwind
Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -340,6 +340,7 @@
void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1329,6 +1329,7 @@
case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
case ISD::CTTZ_ZERO_UNDEF:
case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
+ case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
@@ -2017,6 +2018,19 @@
Hi = DAG.getConstant(0, dl, NVT);
}
+void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDLoc dl(N);
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ unsigned NBitWidth = NVT.getSizeInBits();
+
+ EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
+ Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, NVT);
+ // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
+ DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
+}
+
void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDLoc dl(N);
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