[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Junmo Park via llvm-commits]

flyingforyou added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll:2
@@ -1,1 +1,3 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
+; The instruction latencies of Exynos-M1 triggers the transform we see under the Exynos check.
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I think more proper check-prefix is `EXYNOSM1`, if future exynos core has a possibility that can be different from now.


https://reviews.llvm.org/D21571