[PATCH] D24631: [RFC] Implement variable-width register classes, step 1: API changes

[Krzysztof Parzyszek via llvm-commits]

kparzysz added a comment.

In https://reviews.llvm.org/D24631#544549, @asb wrote:

> Having a register class with a non-constant register size and alignment would solve the issue for HVX, but there's also the hope it will be useful for other targets.


That's a requirement!  :)

Most HVX instructions don't have patterns defining them, since they correspond to fairly complex operations.  For C/C++ programmers, the current HVX programming model is to use intrinsics, and those we do map to HVX instructions. An alternative is to use Halide (which under the covers also generates intrinsics). At the moment, the compiler does not perform any auto-vectorization to use HVX.

This explains the absence of patterns for HVX, but many core Hexagon instructions lack patterns in instruction definitions as well. Instead, we use the "Pat" class. For the purpose of this effort, that may be the preferred approach, since pats are more amenable to various types of annotations. In particular, you can use a "Predicate" object to decide whether a pat should apply or not.  The solution I have in mind for the .td format is based on the predicates to determine the hardware mode, and for patterns it would amount to a syntactic sugar for multiple pats, each predicated on its own predicate for each hardware mode.  An instruction definition also has a list of predicates, but they only enable or disable the single defining pattern: any alternatives need to be provided via pats.

I hope this addresses this part as well:

> For these HVX instructions there is no `list<dag> pattern` defined. If a pattern was specified, surely even with this new functionality you'd need to have repeated instruction definitions in order to define multiple patterns, because they would need different `ValueType`s? Do you have something in mind that would address this as well?



Repository:
  rL LLVM

https://reviews.llvm.org/D24631