[PATCH] D24631: [RFC] Implement variable-width register classes, step 1: API changes

[Krzysztof Parzyszek via llvm-commits]

kparzysz added a comment.

In https://reviews.llvm.org/D24631#544247, @MatzeB wrote:

> - A register in the scheme here should still have a definite encoding, so it should be possible to not require this knowledge at all in the MC layer. Are there other ways to rewrite AMDGPU (like looking which register class a register belongs to determine the size?) I would consider the register size/spillslot properties a part of the TargetRegisterInfo here.


I published a patch for that: https://reviews.llvm.org/D24675.

> - I would not add proxy calls in MachineRegisterInfo. MRI is there to deal with things related to virtual registers not necessarily register classes IMO.


Sure, with the transition to having all this information defined at the TargetRegisterInfo level, there should not be any need for them.  There isn't any need anyway even with this code, I just added it to make the changes a bit shorter.

> - You get instances of TargetRegisterInfo from the TargetSubtargetInfo anyway, so it should not be necessary to pass the SubtargetInfo around to the various calls. Instead you should be able to create specialized TargetRegisterInfo instances for the different sizes in TargetSubtargetInfo::getRegisterInfo().


Good idea.


Repository:
  rL LLVM

https://reviews.llvm.org/D24631