[llvm] r280809 - [X86][SSE] Added and+or combine tests currently failing with vectors

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Sep  7 08:40:03 2016
New Revision: 280809

URL: http://llvm.org/viewvc/llvm-project?rev=280809&view=rev
Log:
[X86][SSE] Added and+or combine tests currently failing with vectors

(and (or x, C), D) -> D if (C & D) == D

Part of the yak shaving for D24253

Modified:
    llvm/trunk/test/CodeGen/X86/combine-and.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-and.ll?rev=280809&r1=280808&r2=280809&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-and.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-and.ll Wed Sep  7 08:40:03 2016
@@ -1,10 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s
+
 ;
 ; Verify that the DAGCombiner is able to fold a vector AND into a blend
 ; if one of the operands to the AND is a vector of all constants, and each
 ; constant element is either zero or all-ones.
-
+;
 
 define <4 x i32> @test1(<4 x i32> %A) {
 ; CHECK-LABEL: test1:
@@ -177,3 +178,29 @@ define <4 x i32> @test17(<4 x i32> %A, <
   %3 = or <4 x i32> %1, %2
   ret <4 x i32> %3
 }
+
+;
+; fold (and (or x, C), D) -> D if (C & D) == D
+;
+
+define <2 x i64> @and_or_v2i64(<2 x i64> %a0) {
+; CHECK-LABEL: and_or_v2i64:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = or <2 x i64> %a0, <i64 255, i64 255>
+  %2 = and <2 x i64> %1, <i64 8, i64 8>
+  ret <2 x i64> %2
+}
+
+define <4 x i32> @and_or_v4i32(<4 x i32> %a0) {
+; CHECK-LABEL: and_or_v4i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = or <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
+  %2 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
+  ret <4 x i32> %2
+}