[llvm] r280736 - [AArch64] Adjust the scheduling model for Exynos M1.
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 6 12:22:29 PDT 2016
Author: evandro
Date: Tue Sep 6 14:22:29 2016
New Revision: 280736
URL: http://llvm.org/viewvc/llvm-project?rev=280736&view=rev
Log:
[AArch64] Adjust the scheduling model for Exynos M1.
Further refine the model for branches.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=280736&r1=280735&r2=280736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Tue Sep 6 14:22:29 2016
@@ -65,6 +65,11 @@ let SchedModel = ExynosM1Model in {
// Coarse scheduling model for the Exynos-M1.
def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
+def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; }
+def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
+def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
+
+def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
def M1WriteLA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
@@ -73,6 +78,7 @@ def M1WriteLA : SchedWriteVariant<[Sched
def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
+def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
def M1WriteSA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
M1WriteA1]>,
SchedVar<NoSchedPred, [M1WriteS1]>]>;
@@ -203,17 +209,6 @@ def M1WriteNEONJ : SchedWriteRes<[M1Un
M1UnitFMAC]> { let Latency = 6; }
def M1WriteNEONK : SchedWriteRes<[M1UnitNMISC,
M1UnitFMAC]> { let Latency = 7; }
-def M1WriteALU1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
-def M1WriteB : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
-// FIXME: This is the worst case, conditional branch and link.
-def M1WriteBL : SchedWriteRes<[M1UnitB,
- M1UnitALU]> { let Latency = 1; }
-// FIXME: This is the worst case, when using LR.
-def M1WriteBLR : SchedWriteRes<[M1UnitB,
- M1UnitALU,
- M1UnitALU]> { let Latency = 2; }
-def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
-def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
def M1WriteFADD3 : SchedWriteRes<[M1UnitFADD]> { let Latency = 3; }
def M1WriteFCVT3 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 3; }
def M1WriteFCVT4 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 4; }
@@ -234,19 +229,22 @@ def M1WriteNMISC1 : SchedWriteRes<[M1Un
def M1WriteNMISC2 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 2; }
def M1WriteNMISC3 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 3; }
def M1WriteNMISC4 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 4; }
-def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
def M1WriteTB : SchedWriteRes<[M1UnitC,
M1UnitALU]> { let Latency = 2; }
// Branch instructions
-def : InstRW<[M1WriteB], (instrs Bcc)>;
-def : InstRW<[M1WriteBL], (instrs BL)>;
-def : InstRW<[M1WriteBLR], (instrs BLR)>;
-def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
-def : InstRW<[M1WriteTB], (instregex "^TBN?Z[WX]")>;
+def : InstRW<[M1WriteB1], (instrs Bcc)>;
+// NOTE: Conditional branch and link adds a B uop.
+def : InstRW<[M1WriteA1], (instrs BL)>;
+// NOTE: Indirect branch and link with LR adds an ALU uop.
+def : InstRW<[M1WriteA1,
+ M1WriteC1], (instrs BLR)>;
+def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
+def : InstRW<[M1WriteC1,
+ M1WriteA2], (instregex "^TBN?Z[WX]")>;
// Arithmetic and logical integer instructions.
-def : InstRW<[M1WriteALU1], (instrs COPY)>;
+def : InstRW<[M1WriteA1], (instrs COPY)>;
// Divide and multiply instructions.
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