[llvm] r280735 - [AArch64] Adjust the scheduling model for Exynos M1.
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 6 12:22:27 PDT 2016
Author: evandro
Date: Tue Sep 6 14:22:27 2016
New Revision: 280735
URL: http://llvm.org/viewvc/llvm-project?rev=280735&view=rev
Log:
[AArch64] Adjust the scheduling model for Exynos M1.
Further refine the model for stores.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=280735&r1=280734&r2=280735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Tue Sep 6 14:22:27 2016
@@ -71,6 +71,12 @@ def M1WriteLA : SchedWriteVariant<[Sched
M1WriteA1]>,
SchedVar<NoSchedPred, [M1WriteL5]>]>;
+def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
+def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
+def M1WriteSA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
+ M1WriteA1]>,
+ SchedVar<NoSchedPred, [M1WriteS1]>]>;
+
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
@@ -117,10 +123,9 @@ def : SchedAlias<WriteLDIdx, M1WriteLA>;
// Store instructions.
def : WriteRes<WriteST, [M1UnitS]> { let Latency = 1; }
-// TODO: Extended address requires also the ALU.
-def : WriteRes<WriteSTIdx, [M1UnitS]> { let Latency = 1; }
def : WriteRes<WriteSTP, [M1UnitS]> { let Latency = 1; }
def : WriteRes<WriteSTX, [M1UnitS]> { let Latency = 1; }
+def : SchedAlias<WriteSTIdx, M1WriteSA>;
// FP data instructions.
def : WriteRes<WriteF, [M1UnitFADD]> { let Latency = 3; }
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