[llvm] r279676 - MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 24 17:14:36 PDT 2016
Already fixed by the followup in r279679
- Matthias
> On Aug 24, 2016, at 4:05 PM, Vitaly Buka <vitalybuka at google.com> wrote:
>
> Should be related to this patch: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15783/steps/check-llvm%20msan/logs/stdio <http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15783/steps/check-llvm%20msan/logs/stdio>
>
> On Wed, Aug 24, 2016 at 3:25 PM Matthias Braun via llvm-commits <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
> Author: matze
> Date: Wed Aug 24 17:17:45 2016
> New Revision: 279676
>
> URL: http://llvm.org/viewvc/llvm-project?rev=279676&view=rev <http://llvm.org/viewvc/llvm-project?rev=279676&view=rev>
> Log:
> MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
>
> tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there
> is not need to change it or save/parse it in a .mir file.
> Make the field const and move the initialization LiveIntervalAnalysis to the
> MachineRegisterInfo constructor. Also cleanup some code and fix some
> instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead
> of TargetSubtargetInfo::enableSubRegLiveness().
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
> llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
> llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
> llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
> llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
> llvm/trunk/lib/CodeGen/MIRPrinter.cpp
> llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
> llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp
> llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
> llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
> llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
> llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
> llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
> llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
> llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
> llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
> llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir
> llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
> llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
> llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
> llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
> llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
> llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
> llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
> llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
>
> Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Wed Aug 24 17:17:45 2016
> @@ -390,7 +390,6 @@ struct MachineFunction {
> bool Selected = false;
> // Register information
> bool TracksRegLiveness = false;
> - bool TracksSubRegLiveness = false;
> std::vector<VirtualRegisterDefinition> VirtualRegisters;
> std::vector<MachineFunctionLiveIn> LiveIns;
> Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
> @@ -415,7 +414,6 @@ template <> struct MappingTraits<Machine
> YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
> YamlIO.mapOptional("selected", MF.Selected);
> YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
> - YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
> YamlIO.mapOptional("registers", MF.VirtualRegisters);
> YamlIO.mapOptional("liveins", MF.LiveIns);
> YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Wed Aug 24 17:17:45 2016
> @@ -51,7 +51,7 @@ private:
> Delegate *TheDelegate;
>
> /// True if subregister liveness is tracked.
> - bool TracksSubRegLiveness;
> + const bool TracksSubRegLiveness;
>
> /// VRegInfo - Information we keep for each virtual register.
> ///
> @@ -199,10 +199,6 @@ public:
> return TracksSubRegLiveness;
> }
>
> - void enableSubRegLiveness(bool Enable = true) {
> - TracksSubRegLiveness = Enable;
> - }
> -
> //===--------------------------------------------------------------------===//
> // Register Info
> //===--------------------------------------------------------------------===//
>
> Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Wed Aug 24 17:17:45 2016
> @@ -218,6 +218,8 @@ public:
> }
>
> /// Enable tracking of subregister liveness in register allocator.
> + /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
> + /// possible.
> virtual bool enableSubRegLiveness() const { return false; }
> };
>
>
> Modified: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp Wed Aug 24 17:17:45 2016
> @@ -577,12 +577,12 @@ bool DetectDeadLanes::runOnMachineFuncti
> // register coalescer cannot deal with hidden dead defs. However without
> // subregister liveness enabled, the expected benefits of this pass are small
> // so we safe the compile time.
> - if (!MF.getSubtarget().enableSubRegLiveness()) {
> + MRI = &MF.getRegInfo();
> + if (!MRI->subRegLivenessEnabled()) {
> DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
> return false;
> }
>
> - MRI = &MF.getRegInfo();
> TRI = MRI->getTargetRegisterInfo();
>
> unsigned NumVirtRegs = MRI->getNumVirtRegs();
>
> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Aug 24 17:17:45 2016
> @@ -58,10 +58,6 @@ static cl::opt<bool> EnablePrecomputePhy
> static bool EnablePrecomputePhysRegs = false;
> #endif // NDEBUG
>
> -static cl::opt<bool> EnableSubRegLiveness(
> - "enable-subreg-liveness", cl::Hidden, cl::init(true),
> - cl::desc("Enable subregister liveness tracking."));
> -
> namespace llvm {
> cl::opt<bool> UseSegmentSetForPhysRegs(
> "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
> @@ -119,9 +115,6 @@ bool LiveIntervals::runOnMachineFunction
> Indexes = &getAnalysis<SlotIndexes>();
> DomTree = &getAnalysis<MachineDominatorTree>();
>
> - if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
> - MRI->enableSubRegLiveness(true);
> -
> if (!LRCalc)
> LRCalc = new LiveRangeCalc();
>
>
> Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Wed Aug 24 17:17:45 2016
> @@ -401,7 +401,6 @@ bool MIRParserImpl::initializeRegisterIn
> assert(RegInfo.tracksLiveness());
> if (!YamlMF.TracksRegLiveness)
> RegInfo.invalidateLiveness();
> - RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
>
> SMDiagnostic Error;
> // Parse the virtual register information.
>
> Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Wed Aug 24 17:17:45 2016
> @@ -213,7 +213,6 @@ void MIRPrinter::convert(yaml::MachineFu
> const MachineRegisterInfo &RegInfo,
> const TargetRegisterInfo *TRI) {
> MF.TracksRegLiveness = RegInfo.tracksLiveness();
> - MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
>
> // Print the virtual register definitions.
> for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
>
> Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Wed Aug 24 17:17:45 2016
> @@ -21,11 +21,16 @@
>
> using namespace llvm;
>
> +static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
> + cl::init(true), cl::desc("Enable subregister liveness tracking."));
> +
> // Pin the vtable to this file.
> void MachineRegisterInfo::Delegate::anchor() {}
>
> MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
> - : MF(MF), TheDelegate(nullptr), TracksSubRegLiveness(false) {
> + : MF(MF), TheDelegate(nullptr),
> + TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
> + EnableSubRegLiveness) {
> unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
> VRegInfo.reserve(256);
> RegAllocHints.reserve(256);
>
> Modified: llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp Wed Aug 24 17:17:45 2016
> @@ -363,14 +363,14 @@ void RenameIndependentSubregs::computeMa
>
> bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) {
> // Skip renaming if liveness of subregister is not tracked.
> - if (!MF.getSubtarget().enableSubRegLiveness())
> + MRI = &MF.getRegInfo();
> + if (!MRI->subRegLivenessEnabled())
> return false;
>
> DEBUG(dbgs() << "Renaming independent subregister live ranges in "
> << MF.getName() << '\n');
>
> LIS = &getAnalysis<LiveIntervals>();
> - MRI = &MF.getRegInfo();
> TII = MF.getSubtarget().getInstrInfo();
>
> // Iterate over all vregs. Note that we query getNumVirtRegs() the newly
>
> Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir (original)
> +++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir Wed Aug 24 17:17:45 2016
> @@ -31,7 +31,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: false
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%x0' }
> - { reg: '%w1' }
> @@ -88,7 +87,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: false
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%x0' }
> - { reg: '%w1' }
>
> Modified: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir (original)
> +++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir Wed Aug 24 17:17:45 2016
> @@ -18,7 +18,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: false
> -tracksSubRegLiveness: false
> frameInfo:
> isFrameAddressTaken: false
> isReturnAddressTaken: false
>
> Modified: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir (original)
> +++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir Wed Aug 24 17:17:45 2016
> @@ -82,7 +82,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%r0' }
> - { reg: '%r1' }
>
> Modified: llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir Wed Aug 24 17:17:45 2016
> @@ -36,7 +36,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: false
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%w0' }
> frameInfo:
>
> Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir Wed Aug 24 17:17:45 2016
> @@ -32,8 +32,7 @@
>
> ...
> ---
> -name: float
> -tracksSubRegLiveness: true
> +name: float
> liveins:
> - { reg: '%sgpr0_sgpr1' }
> frameInfo:
>
> Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir Wed Aug 24 17:17:45 2016
> @@ -32,8 +32,7 @@
>
> ...
> ---
> -name: float
> -tracksSubRegLiveness: true
> +name: float
> liveins:
> - { reg: '%sgpr0_sgpr1' }
> frameInfo:
>
> Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir Wed Aug 24 17:17:45 2016
> @@ -41,8 +41,7 @@
>
> ...
> ---
> -name: float
> -tracksSubRegLiveness: true
> +name: float
> liveins:
> - { reg: '%sgpr0_sgpr1' }
> frameInfo:
> @@ -72,8 +71,7 @@ body: |
> S_ENDPGM
> ...
> ---
> -name: float2
> -tracksSubRegLiveness: true
> +name: float2
> liveins:
> - { reg: '%sgpr0_sgpr1' }
> frameInfo:
>
> Modified: llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir Wed Aug 24 17:17:45 2016
> @@ -93,7 +93,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%r0' }
> - { reg: '%r1' }
>
> Modified: llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir Wed Aug 24 17:17:45 2016
> @@ -18,7 +18,6 @@
> ---
> # CHECK: name: foo
> # CHECK: tracksRegLiveness: false
> -# CHECK-NEXT: tracksSubRegLiveness: false
> # CHECK: ...
> name: foo
> body: |
> @@ -27,11 +26,9 @@ body: |
> ---
> # CHECK: name: bar
> # CHECK: tracksRegLiveness: true
> -# CHECK-NEXT: tracksSubRegLiveness: true
> # CHECK: ...
> name: bar
> tracksRegLiveness: true
> -tracksSubRegLiveness: true
> body: |
> bb.0:
> ...
>
> Modified: llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir Wed Aug 24 17:17:45 2016
> @@ -178,7 +178,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -225,7 +224,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -270,7 +268,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -319,7 +316,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -368,7 +364,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -417,7 +412,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -466,7 +460,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -515,7 +508,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
> @@ -628,7 +620,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: gpr }
> - { id: 1, class: gpr }
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir Wed Aug 24 17:17:45 2016
> @@ -47,7 +47,6 @@ exposesReturnsTwice: false
> hasInlineAsm: true
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%x3' }
> - { reg: '%x4' }
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir Wed Aug 24 17:17:45 2016
> @@ -29,7 +29,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> frameInfo:
> isFrameAddressTaken: false
> isReturnAddressTaken: false
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir Wed Aug 24 17:17:45 2016
> @@ -41,7 +41,6 @@ alignment: 2
> exposesReturnsTwice: false
> hasInlineAsm: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: g8rc_and_g8rc_nox0 }
> - { id: 1, class: g8rc_and_g8rc_nox0 }
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir Wed Aug 24 17:17:45 2016
> @@ -35,7 +35,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: false
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> registers:
> - { id: 0, class: g8rc }
> - { id: 1, class: g8rc }
>
> Modified: llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir (original)
> +++ llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir Wed Aug 24 17:17:45 2016
> @@ -87,7 +87,6 @@ name: imp_null_check_with_bit
> alignment: 4
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%rdi' }
> - { reg: '%esi' }
> @@ -131,7 +130,6 @@ name: imp_null_check_with_bit
> alignment: 4
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%rdi' }
> - { reg: '%esi' }
> @@ -180,7 +178,6 @@ name: imp_null_check_with_bit
> alignment: 4
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%rdi' }
> - { reg: '%esi' }
> @@ -225,7 +222,6 @@ name: imp_null_check_with_bit
> alignment: 4
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%rdi' }
> - { reg: '%rsi' }
>
> Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir (original)
> +++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir Wed Aug 24 17:17:45 2016
> @@ -160,7 +160,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%edi' }
> - { reg: '%esi' }
>
> Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279676&r1=279675&r2=279676&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279676&r1=279675&r2=279676&view=diff>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)
> +++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Wed Aug 24 17:17:45 2016
> @@ -162,7 +162,6 @@ exposesReturnsTwice: false
> hasInlineAsm: false
> allVRegsAllocated: true
> tracksRegLiveness: true
> -tracksSubRegLiveness: false
> liveins:
> - { reg: '%edi' }
> - { reg: '%rsi' }
>
>
> _______________________________________________
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