<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">Already fixed by the followup in r279679</div><div class=""><br class=""></div><div class="">- Matthias</div><br class=""><div><blockquote type="cite" class=""><div class="">On Aug 24, 2016, at 4:05 PM, Vitaly Buka <<a href="mailto:vitalybuka@google.com" class="">vitalybuka@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Should be related to this patch: <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15783/steps/check-llvm%20msan/logs/stdio" class="">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15783/steps/check-llvm%20msan/logs/stdio</a><br class=""></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Wed, Aug 24, 2016 at 3:25 PM Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br class="">
Date: Wed Aug 24 17:17:45 2016<br class="">
New Revision: 279676<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=279676&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=279676&view=rev</a><br class="">
Log:<br class="">
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it<br class="">
<br class="">
tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there<br class="">
is not need to change it or save/parse it in a .mir file.<br class="">
Make the field const and move the initialization LiveIntervalAnalysis to the<br class="">
MachineRegisterInfo constructor. Also cleanup some code and fix some<br class="">
instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead<br class="">
of TargetSubtargetInfo::enableSubRegLiveness().<br class="">
<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br class="">
llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h<br class="">
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h<br class="">
llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp<br class="">
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp<br class="">
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br class="">
llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br class="">
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp<br class="">
llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp<br class="">
llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir<br class="">
llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir<br class="">
llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir<br class="">
llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir<br class="">
llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir<br class="">
llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir<br class="">
llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir<br class="">
llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir<br class="">
llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir<br class="">
llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir<br class="">
llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir<br class="">
llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir<br class="">
llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir<br class="">
llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir<br class="">
llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir<br class="">
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir<br class="">
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Wed Aug 24 17:17:45 2016<br class="">
@@ -390,7 +390,6 @@ struct MachineFunction {<br class="">
bool Selected = false;<br class="">
// Register information<br class="">
bool TracksRegLiveness = false;<br class="">
- bool TracksSubRegLiveness = false;<br class="">
std::vector<VirtualRegisterDefinition> VirtualRegisters;<br class="">
std::vector<MachineFunctionLiveIn> LiveIns;<br class="">
Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;<br class="">
@@ -415,7 +414,6 @@ template <> struct MappingTraits<Machine<br class="">
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);<br class="">
YamlIO.mapOptional("selected", MF.Selected);<br class="">
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);<br class="">
- YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);<br class="">
YamlIO.mapOptional("registers", MF.VirtualRegisters);<br class="">
YamlIO.mapOptional("liveins", MF.LiveIns);<br class="">
YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Wed Aug 24 17:17:45 2016<br class="">
@@ -51,7 +51,7 @@ private:<br class="">
Delegate *TheDelegate;<br class="">
<br class="">
/// True if subregister liveness is tracked.<br class="">
- bool TracksSubRegLiveness;<br class="">
+ const bool TracksSubRegLiveness;<br class="">
<br class="">
/// VRegInfo - Information we keep for each virtual register.<br class="">
///<br class="">
@@ -199,10 +199,6 @@ public:<br class="">
return TracksSubRegLiveness;<br class="">
}<br class="">
<br class="">
- void enableSubRegLiveness(bool Enable = true) {<br class="">
- TracksSubRegLiveness = Enable;<br class="">
- }<br class="">
-<br class="">
//===--------------------------------------------------------------------===//<br class="">
// Register Info<br class="">
//===--------------------------------------------------------------------===//<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)<br class="">
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Wed Aug 24 17:17:45 2016<br class="">
@@ -218,6 +218,8 @@ public:<br class="">
}<br class="">
<br class="">
/// Enable tracking of subregister liveness in register allocator.<br class="">
+ /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where<br class="">
+ /// possible.<br class="">
virtual bool enableSubRegLiveness() const { return false; }<br class="">
};<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp Wed Aug 24 17:17:45 2016<br class="">
@@ -577,12 +577,12 @@ bool DetectDeadLanes::runOnMachineFuncti<br class="">
// register coalescer cannot deal with hidden dead defs. However without<br class="">
// subregister liveness enabled, the expected benefits of this pass are small<br class="">
// so we safe the compile time.<br class="">
- if (!MF.getSubtarget().enableSubRegLiveness()) {<br class="">
+ MRI = &MF.getRegInfo();<br class="">
+ if (!MRI->subRegLivenessEnabled()) {<br class="">
DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");<br class="">
return false;<br class="">
}<br class="">
<br class="">
- MRI = &MF.getRegInfo();<br class="">
TRI = MRI->getTargetRegisterInfo();<br class="">
<br class="">
unsigned NumVirtRegs = MRI->getNumVirtRegs();<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Aug 24 17:17:45 2016<br class="">
@@ -58,10 +58,6 @@ static cl::opt<bool> EnablePrecomputePhy<br class="">
static bool EnablePrecomputePhysRegs = false;<br class="">
#endif // NDEBUG<br class="">
<br class="">
-static cl::opt<bool> EnableSubRegLiveness(<br class="">
- "enable-subreg-liveness", cl::Hidden, cl::init(true),<br class="">
- cl::desc("Enable subregister liveness tracking."));<br class="">
-<br class="">
namespace llvm {<br class="">
cl::opt<bool> UseSegmentSetForPhysRegs(<br class="">
"use-segment-set-for-physregs", cl::Hidden, cl::init(true),<br class="">
@@ -119,9 +115,6 @@ bool LiveIntervals::runOnMachineFunction<br class="">
Indexes = &getAnalysis<SlotIndexes>();<br class="">
DomTree = &getAnalysis<MachineDominatorTree>();<br class="">
<br class="">
- if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())<br class="">
- MRI->enableSubRegLiveness(true);<br class="">
-<br class="">
if (!LRCalc)<br class="">
LRCalc = new LiveRangeCalc();<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Wed Aug 24 17:17:45 2016<br class="">
@@ -401,7 +401,6 @@ bool MIRParserImpl::initializeRegisterIn<br class="">
assert(RegInfo.tracksLiveness());<br class="">
if (!YamlMF.TracksRegLiveness)<br class="">
RegInfo.invalidateLiveness();<br class="">
- RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);<br class="">
<br class="">
SMDiagnostic Error;<br class="">
// Parse the virtual register information.<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Wed Aug 24 17:17:45 2016<br class="">
@@ -213,7 +213,6 @@ void MIRPrinter::convert(yaml::MachineFu<br class="">
const MachineRegisterInfo &RegInfo,<br class="">
const TargetRegisterInfo *TRI) {<br class="">
MF.TracksRegLiveness = RegInfo.tracksLiveness();<br class="">
- MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();<br class="">
<br class="">
// Print the virtual register definitions.<br class="">
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Wed Aug 24 17:17:45 2016<br class="">
@@ -21,11 +21,16 @@<br class="">
<br class="">
using namespace llvm;<br class="">
<br class="">
+static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,<br class="">
+ cl::init(true), cl::desc("Enable subregister liveness tracking."));<br class="">
+<br class="">
// Pin the vtable to this file.<br class="">
void MachineRegisterInfo::Delegate::anchor() {}<br class="">
<br class="">
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)<br class="">
- : MF(MF), TheDelegate(nullptr), TracksSubRegLiveness(false) {<br class="">
+ : MF(MF), TheDelegate(nullptr),<br class="">
+ TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&<br class="">
+ EnableSubRegLiveness) {<br class="">
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();<br class="">
VRegInfo.reserve(256);<br class="">
RegAllocHints.reserve(256);<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp Wed Aug 24 17:17:45 2016<br class="">
@@ -363,14 +363,14 @@ void RenameIndependentSubregs::computeMa<br class="">
<br class="">
bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) {<br class="">
// Skip renaming if liveness of subregister is not tracked.<br class="">
- if (!MF.getSubtarget().enableSubRegLiveness())<br class="">
+ MRI = &MF.getRegInfo();<br class="">
+ if (!MRI->subRegLivenessEnabled())<br class="">
return false;<br class="">
<br class="">
DEBUG(dbgs() << "Renaming independent subregister live ranges in "<br class="">
<< MF.getName() << '\n');<br class="">
<br class="">
LIS = &getAnalysis<LiveIntervals>();<br class="">
- MRI = &MF.getRegInfo();<br class="">
TII = MF.getSubtarget().getInstrInfo();<br class="">
<br class="">
// Iterate over all vregs. Note that we query getNumVirtRegs() the newly<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -31,7 +31,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: false<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%x0' }<br class="">
- { reg: '%w1' }<br class="">
@@ -88,7 +87,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: false<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%x0' }<br class="">
- { reg: '%w1' }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -18,7 +18,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: false<br class="">
-tracksSubRegLiveness: false<br class="">
frameInfo:<br class="">
isFrameAddressTaken: false<br class="">
isReturnAddressTaken: false<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -82,7 +82,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%r0' }<br class="">
- { reg: '%r1' }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -36,7 +36,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: false<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%w0' }<br class="">
frameInfo:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -32,8 +32,7 @@<br class="">
<br class="">
...<br class="">
---<br class="">
-name: float<br class="">
-tracksSubRegLiveness: true<br class="">
+name: float<br class="">
liveins:<br class="">
- { reg: '%sgpr0_sgpr1' }<br class="">
frameInfo:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -32,8 +32,7 @@<br class="">
<br class="">
...<br class="">
---<br class="">
-name: float<br class="">
-tracksSubRegLiveness: true<br class="">
+name: float<br class="">
liveins:<br class="">
- { reg: '%sgpr0_sgpr1' }<br class="">
frameInfo:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -41,8 +41,7 @@<br class="">
<br class="">
...<br class="">
---<br class="">
-name: float<br class="">
-tracksSubRegLiveness: true<br class="">
+name: float<br class="">
liveins:<br class="">
- { reg: '%sgpr0_sgpr1' }<br class="">
frameInfo:<br class="">
@@ -72,8 +71,7 @@ body: |<br class="">
S_ENDPGM<br class="">
...<br class="">
---<br class="">
-name: float2<br class="">
-tracksSubRegLiveness: true<br class="">
+name: float2<br class="">
liveins:<br class="">
- { reg: '%sgpr0_sgpr1' }<br class="">
frameInfo:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -93,7 +93,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%r0' }<br class="">
- { reg: '%r1' }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -18,7 +18,6 @@<br class="">
---<br class="">
# CHECK: name: foo<br class="">
# CHECK: tracksRegLiveness: false<br class="">
-# CHECK-NEXT: tracksSubRegLiveness: false<br class="">
# CHECK: ...<br class="">
name: foo<br class="">
body: |<br class="">
@@ -27,11 +26,9 @@ body: |<br class="">
---<br class="">
# CHECK: name: bar<br class="">
# CHECK: tracksRegLiveness: true<br class="">
-# CHECK-NEXT: tracksSubRegLiveness: true<br class="">
# CHECK: ...<br class="">
name: bar<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: true<br class="">
body: |<br class="">
bb.0:<br class="">
...<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -178,7 +178,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -225,7 +224,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -270,7 +268,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -319,7 +316,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -368,7 +364,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -417,7 +412,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -466,7 +460,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -515,7 +508,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
@@ -628,7 +620,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: gpr }<br class="">
- { id: 1, class: gpr }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -47,7 +47,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: true<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%x3' }<br class="">
- { reg: '%x4' }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -29,7 +29,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
frameInfo:<br class="">
isFrameAddressTaken: false<br class="">
isReturnAddressTaken: false<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -41,7 +41,6 @@ alignment: 2<br class="">
exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: g8rc_and_g8rc_nox0 }<br class="">
- { id: 1, class: g8rc_and_g8rc_nox0 }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -35,7 +35,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: false<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
registers:<br class="">
- { id: 0, class: g8rc }<br class="">
- { id: 1, class: g8rc }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -87,7 +87,6 @@ name: imp_null_check_with_bit<br class="">
alignment: 4<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%rdi' }<br class="">
- { reg: '%esi' }<br class="">
@@ -131,7 +130,6 @@ name: imp_null_check_with_bit<br class="">
alignment: 4<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%rdi' }<br class="">
- { reg: '%esi' }<br class="">
@@ -180,7 +178,6 @@ name: imp_null_check_with_bit<br class="">
alignment: 4<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%rdi' }<br class="">
- { reg: '%esi' }<br class="">
@@ -225,7 +222,6 @@ name: imp_null_check_with_bit<br class="">
alignment: 4<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%rdi' }<br class="">
- { reg: '%rsi' }<br class="">
<br class="">
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir (original)<br class="">
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -160,7 +160,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%edi' }<br class="">
- { reg: '%esi' }<br class="">
<br class="">
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)<br class="">
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Wed Aug 24 17:17:45 2016<br class="">
@@ -162,7 +162,6 @@ exposesReturnsTwice: false<br class="">
hasInlineAsm: false<br class="">
allVRegsAllocated: true<br class="">
tracksRegLiveness: true<br class="">
-tracksSubRegLiveness: false<br class="">
liveins:<br class="">
- { reg: '%edi' }<br class="">
- { reg: '%rsi' }<br class="">
<br class="">
<br class="">
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