[llvm] r279573 - MachineFunction: Introduce NoPHIs property

Vitaly Buka via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 23 15:13:32 PDT 2016


This patch?
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/9417/steps/ninja%20check%201/logs/stdio

On Tue, Aug 23, 2016 at 2:27 PM Matthias Braun via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: matze
> Date: Tue Aug 23 16:19:49 2016
> New Revision: 279573
>
> URL: http://llvm.org/viewvc/llvm-project?rev=279573&view=rev
> Log:
> MachineFunction: Introduce NoPHIs property
>
> I want to compute the SSA property of .mir files automatically in
> upcoming patches. The problem with this is that some inputs will be
> reported as static single assignment with some passes claiming not to
> support SSA form.  In reality though those passes do not support PHI
> instructions => Track the presence of PHI instructions separate from the
> SSA property.
>
> Differential Revision: https://reviews.llvm.org/D22719
>
> Modified:
>     llvm/trunk/include/llvm/CodeGen/MachineFunction.h
>     llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
>     llvm/trunk/lib/CodeGen/MachineFunction.cpp
>     llvm/trunk/lib/CodeGen/MachineVerifier.cpp
>     llvm/trunk/lib/CodeGen/PHIElimination.cpp
>     llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
>     llvm/trunk/lib/CodeGen/RegAllocFast.cpp
>     llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
>     llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
>     llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Aug 23 16:19:49
> 2016
> @@ -92,6 +92,7 @@ public:
>    // Property descriptions:
>    // IsSSA: True when the machine function is in SSA form and virtual
> registers
>    //  have a single def.
> +  // NoPHIs: The machine function does not contain any PHI instruction.
>    // TracksLiveness: True when tracking register liveness accurately.
>    //  While this property is set, register liveness information in basic
> block
>    //  live-in lists and machine instruction operands (e.g. kill flags,
> implicit
> @@ -117,6 +118,7 @@ public:
>    //  all sizes attached to them have been eliminated.
>    enum class Property : unsigned {
>      IsSSA,
> +    NoPHIs,
>      TracksLiveness,
>      AllVRegsAllocated,
>      Legalized,
>
> Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug 23 16:19:49 2016
> @@ -160,6 +160,8 @@ private:
>    ///
>    /// Return null if the name isn't a register bank.
>    const RegisterBank *getRegBank(const MachineFunction &MF, StringRef
> Name);
> +
> +  void computeFunctionProperties(MachineFunction &MF);
>  };
>
>  } // end namespace llvm
> @@ -279,6 +281,19 @@ void MIRParserImpl::createDummyFunction(
>    new UnreachableInst(Context, BB);
>  }
>
> +static bool hasPHI(const MachineFunction &MF) {
> +  for (const MachineBasicBlock &MBB : MF)
> +    for (const MachineInstr &MI : MBB)
> +      if (MI.isPHI())
> +        return true;
> +  return false;
> +}
> +
> +void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
> +  if (!hasPHI(MF))
> +    MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
> +}
> +
>  bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
>    auto It = Functions.find(MF.getName());
>    if (It == Functions.end())
> @@ -353,6 +368,9 @@ bool MIRParserImpl::initializeMachineFun
>    PFS.SM = &SM;
>
>    inferRegisterInfo(PFS, YamlMF);
> +
> +  computeFunctionProperties(MF);
> +
>    // FIXME: This is a temporary workaround until the reserved registers
> can be
>    // serialized.
>    MF.getRegInfo().freezeReservedRegs(MF);
>
> Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Aug 23 16:19:49 2016
> @@ -60,6 +60,7 @@ static const char *getPropertyName(Machi
>    case P::AllVRegsAllocated: return "AllVRegsAllocated";
>    case P::IsSSA: return "IsSSA";
>    case P::Legalized: return "Legalized";
> +  case P::NoPHIs: return "NoPHIs";
>    case P::RegBankSelected: return "RegBankSelected";
>    case P::Selected: return "Selected";
>    case P::TracksLiveness: return "TracksLiveness";
>
> Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Aug 23 16:19:49 2016
> @@ -858,6 +858,10 @@ void MachineVerifier::visitMachineInstrB
>          << MI->getNumOperands() << " given.\n";
>    }
>
> +  if (MI->isPHI() && MF->getProperties().hasProperty(
> +          MachineFunctionProperties::Property::NoPHIs))
> +    report("Found PHI instruction with NoPHIs property set", MI);
> +
>    // Check the tied operands.
>    if (MI->isInlineAsm())
>      verifyInlineAsm(MI);
>
> Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
> +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Aug 23 16:19:49 2016
> @@ -175,6 +175,8 @@ bool PHIElimination::runOnMachineFunctio
>    ImpDefs.clear();
>    VRegPHIUseCount.clear();
>
> +  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
> +
>    return Changed;
>  }
>
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Aug 23 16:19:49 2016
> @@ -105,6 +105,11 @@ public:
>    /// Perform register allocation.
>    bool runOnMachineFunction(MachineFunction &mf) override;
>
> +  MachineFunctionProperties getRequiredProperties() const override {
> +    return MachineFunctionProperties().set(
> +        MachineFunctionProperties::Property::NoPHIs);
> +  }
> +
>    // Helper for spilling all live virtual registers currently unified
> under preg
>    // that interfere with the most recently queried lvr.  Return true if
> spilling
>    // was successful, and append any new spilled/split intervals to
> splitLVRs.
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Aug 23 16:19:49 2016
> @@ -158,6 +158,11 @@ namespace {
>        MachineFunctionPass::getAnalysisUsage(AU);
>      }
>
> +    MachineFunctionProperties getRequiredProperties() const override {
> +      return MachineFunctionProperties().set(
> +          MachineFunctionProperties::Property::NoPHIs);
> +    }
> +
>      MachineFunctionProperties getSetProperties() const override {
>        return MachineFunctionProperties().set(
>            MachineFunctionProperties::Property::AllVRegsAllocated);
> @@ -1093,8 +1098,6 @@ bool RAFast::runOnMachineFunction(Machin
>    UsedInInstr.clear();
>    UsedInInstr.setUniverse(TRI->getNumRegUnits());
>
> -  assert(!MRI->isSSA() && "regalloc requires leaving SSA");
> -
>    // initialize the virtual->physical register map to have a 'null'
>    // mapping for all virtual registers
>    StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Aug 23 16:19:49 2016
> @@ -334,6 +334,11 @@ public:
>    /// Perform register allocation.
>    bool runOnMachineFunction(MachineFunction &mf) override;
>
> +  MachineFunctionProperties getRequiredProperties() const override {
> +    return MachineFunctionProperties().set(
> +        MachineFunctionProperties::Property::NoPHIs);
> +  }
> +
>    static char ID;
>
>  private:
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Aug 23 16:19:49 2016
> @@ -109,6 +109,11 @@ public:
>    /// Perform register allocation
>    bool runOnMachineFunction(MachineFunction &MF) override;
>
> +  MachineFunctionProperties getRequiredProperties() const override {
> +    return MachineFunctionProperties().set(
> +        MachineFunctionProperties::Property::NoPHIs);
> +  }
> +
>  private:
>
>    typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=279573&r1=279572&r2=279573&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp Tue Aug 23
> 16:19:49 2016
> @@ -98,6 +98,11 @@ public:
>      return "SI Load / Store Optimizer";
>    }
>
> +  MachineFunctionProperties getRequiredProperties() const override {
> +    return MachineFunctionProperties().set(
> +      MachineFunctionProperties::Property::NoPHIs);
> +  }
> +
>    void getAnalysisUsage(AnalysisUsage &AU) const override {
>      AU.setPreservesCFG();
>      AU.addPreserved<SlotIndexes>();
> @@ -425,8 +430,6 @@ bool SILoadStoreOptimizer::runOnMachineF
>
>    DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
>
> -  assert(!MRI->isSSA());
> -
>    bool Modified = false;
>
>    for (MachineBasicBlock &MBB : MF)
>
>
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