<div dir="ltr">This patch? <a href="http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/9417/steps/ninja%20check%201/logs/stdio">http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/9417/steps/ninja%20check%201/logs/stdio</a></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Aug 23, 2016 at 2:27 PM Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br>
Date: Tue Aug 23 16:19:49 2016<br>
New Revision: 279573<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=279573&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=279573&view=rev</a><br>
Log:<br>
MachineFunction: Introduce NoPHIs property<br>
<br>
I want to compute the SSA property of .mir files automatically in<br>
upcoming patches. The problem with this is that some inputs will be<br>
reported as static single assignment with some passes claiming not to<br>
support SSA form. In reality though those passes do not support PHI<br>
instructions => Track the presence of PHI instructions separate from the<br>
SSA property.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D22719" rel="noreferrer" target="_blank">https://reviews.llvm.org/D22719</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MachineFunction.h<br>
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
llvm/trunk/lib/CodeGen/MachineFunction.cpp<br>
llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br>
llvm/trunk/lib/CodeGen/PHIElimination.cpp<br>
llvm/trunk/lib/CodeGen/RegAllocBasic.cpp<br>
llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br>
llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Aug 23 16:19:49 2016<br>
@@ -92,6 +92,7 @@ public:<br>
// Property descriptions:<br>
// IsSSA: True when the machine function is in SSA form and virtual registers<br>
// have a single def.<br>
+ // NoPHIs: The machine function does not contain any PHI instruction.<br>
// TracksLiveness: True when tracking register liveness accurately.<br>
// While this property is set, register liveness information in basic block<br>
// live-in lists and machine instruction operands (e.g. kill flags, implicit<br>
@@ -117,6 +118,7 @@ public:<br>
// all sizes attached to them have been eliminated.<br>
enum class Property : unsigned {<br>
IsSSA,<br>
+ NoPHIs,<br>
TracksLiveness,<br>
AllVRegsAllocated,<br>
Legalized,<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug 23 16:19:49 2016<br>
@@ -160,6 +160,8 @@ private:<br>
///<br>
/// Return null if the name isn't a register bank.<br>
const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);<br>
+<br>
+ void computeFunctionProperties(MachineFunction &MF);<br>
};<br>
<br>
} // end namespace llvm<br>
@@ -279,6 +281,19 @@ void MIRParserImpl::createDummyFunction(<br>
new UnreachableInst(Context, BB);<br>
}<br>
<br>
+static bool hasPHI(const MachineFunction &MF) {<br>
+ for (const MachineBasicBlock &MBB : MF)<br>
+ for (const MachineInstr &MI : MBB)<br>
+ if (MI.isPHI())<br>
+ return true;<br>
+ return false;<br>
+}<br>
+<br>
+void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {<br>
+ if (!hasPHI(MF))<br>
+ MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);<br>
+}<br>
+<br>
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {<br>
auto It = Functions.find(MF.getName());<br>
if (It == Functions.end())<br>
@@ -353,6 +368,9 @@ bool MIRParserImpl::initializeMachineFun<br>
<a href="http://PFS.SM" rel="noreferrer" target="_blank">PFS.SM</a> = &SM;<br>
<br>
inferRegisterInfo(PFS, YamlMF);<br>
+<br>
+ computeFunctionProperties(MF);<br>
+<br>
// FIXME: This is a temporary workaround until the reserved registers can be<br>
// serialized.<br>
MF.getRegInfo().freezeReservedRegs(MF);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Aug 23 16:19:49 2016<br>
@@ -60,6 +60,7 @@ static const char *getPropertyName(Machi<br>
case P::AllVRegsAllocated: return "AllVRegsAllocated";<br>
case P::IsSSA: return "IsSSA";<br>
case P::Legalized: return "Legalized";<br>
+ case P::NoPHIs: return "NoPHIs";<br>
case P::RegBankSelected: return "RegBankSelected";<br>
case P::Selected: return "Selected";<br>
case P::TracksLiveness: return "TracksLiveness";<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Aug 23 16:19:49 2016<br>
@@ -858,6 +858,10 @@ void MachineVerifier::visitMachineInstrB<br>
<< MI->getNumOperands() << " given.\n";<br>
}<br>
<br>
+ if (MI->isPHI() && MF->getProperties().hasProperty(<br>
+ MachineFunctionProperties::Property::NoPHIs))<br>
+ report("Found PHI instruction with NoPHIs property set", MI);<br>
+<br>
// Check the tied operands.<br>
if (MI->isInlineAsm())<br>
verifyInlineAsm(MI);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Aug 23 16:19:49 2016<br>
@@ -175,6 +175,8 @@ bool PHIElimination::runOnMachineFunctio<br>
ImpDefs.clear();<br>
VRegPHIUseCount.clear();<br>
<br>
+ MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);<br>
+<br>
return Changed;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Aug 23 16:19:49 2016<br>
@@ -105,6 +105,11 @@ public:<br>
/// Perform register allocation.<br>
bool runOnMachineFunction(MachineFunction &mf) override;<br>
<br>
+ MachineFunctionProperties getRequiredProperties() const override {<br>
+ return MachineFunctionProperties().set(<br>
+ MachineFunctionProperties::Property::NoPHIs);<br>
+ }<br>
+<br>
// Helper for spilling all live virtual registers currently unified under preg<br>
// that interfere with the most recently queried lvr. Return true if spilling<br>
// was successful, and append any new spilled/split intervals to splitLVRs.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Aug 23 16:19:49 2016<br>
@@ -158,6 +158,11 @@ namespace {<br>
MachineFunctionPass::getAnalysisUsage(AU);<br>
}<br>
<br>
+ MachineFunctionProperties getRequiredProperties() const override {<br>
+ return MachineFunctionProperties().set(<br>
+ MachineFunctionProperties::Property::NoPHIs);<br>
+ }<br>
+<br>
MachineFunctionProperties getSetProperties() const override {<br>
return MachineFunctionProperties().set(<br>
MachineFunctionProperties::Property::AllVRegsAllocated);<br>
@@ -1093,8 +1098,6 @@ bool RAFast::runOnMachineFunction(Machin<br>
UsedInInstr.clear();<br>
UsedInInstr.setUniverse(TRI->getNumRegUnits());<br>
<br>
- assert(!MRI->isSSA() && "regalloc requires leaving SSA");<br>
-<br>
// initialize the virtual->physical register map to have a 'null'<br>
// mapping for all virtual registers<br>
StackSlotForVirtReg.resize(MRI->getNumVirtRegs());<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Aug 23 16:19:49 2016<br>
@@ -334,6 +334,11 @@ public:<br>
/// Perform register allocation.<br>
bool runOnMachineFunction(MachineFunction &mf) override;<br>
<br>
+ MachineFunctionProperties getRequiredProperties() const override {<br>
+ return MachineFunctionProperties().set(<br>
+ MachineFunctionProperties::Property::NoPHIs);<br>
+ }<br>
+<br>
static char ID;<br>
<br>
private:<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Aug 23 16:19:49 2016<br>
@@ -109,6 +109,11 @@ public:<br>
/// Perform register allocation<br>
bool runOnMachineFunction(MachineFunction &MF) override;<br>
<br>
+ MachineFunctionProperties getRequiredProperties() const override {<br>
+ return MachineFunctionProperties().set(<br>
+ MachineFunctionProperties::Property::NoPHIs);<br>
+ }<br>
+<br>
private:<br>
<br>
typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp Tue Aug 23 16:19:49 2016<br>
@@ -98,6 +98,11 @@ public:<br>
return "SI Load / Store Optimizer";<br>
}<br>
<br>
+ MachineFunctionProperties getRequiredProperties() const override {<br>
+ return MachineFunctionProperties().set(<br>
+ MachineFunctionProperties::Property::NoPHIs);<br>
+ }<br>
+<br>
void getAnalysisUsage(AnalysisUsage &AU) const override {<br>
AU.setPreservesCFG();<br>
AU.addPreserved<SlotIndexes>();<br>
@@ -425,8 +430,6 @@ bool SILoadStoreOptimizer::runOnMachineF<br>
<br>
DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");<br>
<br>
- assert(!MRI->isSSA());<br>
-<br>
bool Modified = false;<br>
<br>
for (MachineBasicBlock &MBB : MF)<br>
<br>
<br>
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</blockquote></div>