[PATCH] D23673: [X86][SSE] Add support for 32-bit element vectors to X86ISD::VZEXT_LOAD

[Michael Kuperstein via llvm-commits]

mkuper added a comment.

The code LGTM.
Regarding the rationale - I don't see why this should be different for i32 and i64. But I don't really understand shuffle lowering well enough, so take this with a grain of salt.

We still need the vzmovl patterns because of lowerVectorShuffleAsElementInsertion, right? Do we have anything them tests them now that we will no longer generate these patterns in EltsFromConsecutiveLoads?


Repository:
  rL LLVM

https://reviews.llvm.org/D23673