[PATCH] D23601: [TII] add new target hook isAdd

[Sjoerd Meijer via llvm-commits]

SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: bcahoon, kparzysz, jmolloy.
SjoerdMeijer added a subscriber: llvm-commits.

This adds a new target hook isAdd to TargetInstrInfo. This is refactored from the Hexagon backend and is more groundwork to find induction variables and calculate loop counts on MachineLoops. 

https://reviews.llvm.org/D23601

Files:
  include/llvm/Target/TargetInstrInfo.h
  lib/Target/Hexagon/HexagonHardwareLoops.cpp
  lib/Target/Hexagon/HexagonInstrInfo.cpp
  lib/Target/Hexagon/HexagonInstrInfo.h

Index: lib/Target/Hexagon/HexagonInstrInfo.h
===================================================================
--- lib/Target/Hexagon/HexagonInstrInfo.h
+++ lib/Target/Hexagon/HexagonInstrInfo.h
@@ -208,6 +208,9 @@
   /// Return true for post-incremented instructions.
   bool isPostIncrement(const MachineInstr &MI) const override;
 
+  /// Returns true if the instruction is an add instruction
+  bool isAdd(const MachineInstr &MI) const override;
+
   /// Convert the instruction into a predicated instruction.
   /// It returns true if the operation was successful.
   bool PredicateInstruction(MachineInstr &MI,
Index: lib/Target/Hexagon/HexagonInstrInfo.cpp
===================================================================
--- lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1330,6 +1330,17 @@
 }
 
 
+bool HexagonInstrInfo::isAdd(const MachineInstr &MI) const {
+  switch(MI.getOpcode()) {
+  default:
+    return false;
+  case Hexagon::A2_addi:
+  case Hexagon::A2_addp:
+    return true;
+  }
+}
+
+
 // Returns true if an instruction is predicated irrespective of the predicate
 // sense. For example, all of the following will return true.
 // if (p0) R1 = add(R2, R3)
Index: lib/Target/Hexagon/HexagonHardwareLoops.cpp
===================================================================
--- lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -411,10 +411,8 @@
 
       unsigned PhiOpReg = Phi->getOperand(i).getReg();
       MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
-      unsigned UpdOpc = DI->getOpcode();
-      bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp);
 
-      if (isAdd) {
+      if (TII->isAdd(*DI)) {
         // If the register operand to the add is the PHI we're looking at, this
         // meets the induction pattern.
         unsigned IndReg = DI->getOperand(1).getReg();
@@ -1592,10 +1590,8 @@
 
       unsigned PhiReg = Phi->getOperand(i).getReg();
       MachineInstr *DI = MRI->getVRegDef(PhiReg);
-      unsigned UpdOpc = DI->getOpcode();
-      bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp);
 
-      if (isAdd) {
+      if (TII->isAdd(*DI)) {
         // If the register operand to the add/sub is the PHI we are looking
         // at, this meets the induction pattern.
         unsigned IndReg = DI->getOperand(1).getReg();
Index: include/llvm/Target/TargetInstrInfo.h
===================================================================
--- include/llvm/Target/TargetInstrInfo.h
+++ include/llvm/Target/TargetInstrInfo.h
@@ -1083,6 +1083,11 @@
     return false;
   }
 
+  /// Returns true if the instruction is an add instruction
+  virtual bool isAdd(const MachineInstr &MI) const {
+    return false;
+  }
+
   /// Returns true if the instruction is a
   /// terminator instruction that has not been predicated.
   virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;


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