[PATCH] D22726: [DAGCombine] Match shift amount by value rather than relying on common sub-expressions.
bryant via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 14:15:06 PDT 2016
bryant updated this revision to Diff 68253.
bryant added a comment.
- Reinstate zeroExtendToMatch.
- Use OpSizeInBits instead of recomputing result width.
Repository:
rL LLVM
https://reviews.llvm.org/D22726
Files:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/X86/cmp-zext-combine.ll
Index: test/CodeGen/X86/cmp-zext-combine.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/cmp-zext-combine.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+
+define i32 @nonzero(i32) {
+; CHECK-LABEL: nonzero:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: retq
+ %b = zext i32 %0 to i64
+ %c = shl i64 %b, 32
+ %d = icmp ugt i64 %c, 4294967295
+ %rv = zext i1 %d to i32
+ ret i32 %rv
+}
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4850,13 +4850,18 @@
}
// fold (srl (shl x, c), c) -> (and x, cst2)
- if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
- unsigned BitSize = N0.getScalarValueSizeInBits();
- if (BitSize <= 64) {
- uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
+ if (N1C && N0.getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(N0.getOperand(1))) {
+ APInt c1 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+ APInt c0 = N1C->getAPIntValue();
+ zeroExtendToMatch(c1, c0);
+ if (c1.eq(c0)) {
+ uint64_t MaskWidth =
+ c0.ugt(OpSizeInBits) ? 0 : OpSizeInBits - c0.getZExtValue();
+ APInt Mask = APInt::getLowBitsSet(OpSizeInBits, MaskWidth);
SDLoc DL(N);
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
- DAG.getConstant(~0ULL >> ShAmt, DL, VT));
+ DAG.getConstant(Mask, DL, VT));
}
}
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