[llvm] r278824 - [mips] Enforce compact branch restrictions

[Simon Dardis via llvm-commits]

Author: sdardis
Date: Tue Aug 16 12:16:11 2016
New Revision: 278824

URL: http://llvm.org/viewvc/llvm-project?rev=278824&view=rev
Log:
[mips] Enforce compact branch restrictions

Check both operands for use of the $zero register which cannot be used with
a compact branch instruction.

Reviewers: dsanders, vkalintris

Differential Review: https://reviews.llvm.org/D23547

Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=278824&r1=278823&r2=278824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Aug 16 12:16:11 2016
@@ -426,14 +426,19 @@ MipsInstrInfo::genInstrWithNewOpc(unsign
   // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
   // Pick the zero form of the branch for readable assembly and for greater
   // branch distance in non-microMIPS mode.
+  // Additional MIPSR6 does not permit the use of register $zero for compact
+  // branches.
   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
   // Mips::ZERO, which is incorrect. This test should be updated to use
   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
   // are fixed.
-  bool BranchWithZeroOperand =
-      (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() &&
-       (I->getOperand(1).getReg() == Mips::ZERO ||
-        I->getOperand(1).getReg() == Mips::ZERO_64));
+  int ZeroOperandPosition = -1;
+  bool BranchWithZeroOperand = false;
+  if (I->isBranch() && !I->isPseudo()) {
+    auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
+    ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
+    BranchWithZeroOperand = ZeroOperandPosition != -1;
+  }
 
   if (BranchWithZeroOperand) {
     switch (NewOpc) {
@@ -476,17 +481,11 @@ MipsInstrInfo::genInstrWithNewOpc(unsign
 
     MIB.addImm(0);
 
- } else if (BranchWithZeroOperand) {
-    // For MIPSR6 and microMIPS branches with an explicit zero operand, copy
-    // everything after the zero.
-     MIB.addOperand(I->getOperand(0));
-
-    for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) {
-      MIB.addOperand(I->getOperand(J));
-    }
   } else {
-    // All other cases copy all other operands.
     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
+      if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
+        continue;
+
       MIB.addOperand(I->getOperand(J));
     }
   }

Modified: llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll?rev=278824&r1=278823&r2=278824&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll Tue Aug 16 12:16:11 2016
@@ -100,3 +100,31 @@ define i64 @f5(i64 %a, i64 %b) {
   if.end:
     ret i64 0
 }
+
+define i32 @f6(i32 %a) {
+; CHECK-LABEL: f6:
+; CHECK: beqzc ${{[0-9]+}}, $BB
+
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
+
+define i32 @f7(i32 %a) {
+; CHECK-LABEL: f7:
+; CHECK: bnezc ${{[0-9]+}}, $BB
+
+  %cmp = icmp eq i32 0, %a
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}