[llvm] r278823 - [Hexagon] Clean up some miscellaneous V60 intrinsics a bit
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 10:14:45 PDT 2016
Author: kparzysz
Date: Tue Aug 16 12:14:44 2016
New Revision: 278823
URL: http://llvm.org/viewvc/llvm-project?rev=278823&view=rev
Log:
[Hexagon] Clean up some miscellaneous V60 intrinsics a bit
Modified:
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=278823&r1=278822&r2=278823&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Tue Aug 16 12:14:44 2016
@@ -1642,7 +1642,7 @@ int HexagonAsmParser::processInstruction
}
// Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
- case Hexagon::HEXAGON_V6_vassignpair: {
+ case Hexagon::V6_vassignp: {
MCOperand &MO = Inst.getOperand(1);
unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
std::string R1 = v + llvm::utostr(RegPairNum + 1);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=278823&r1=278822&r2=278823&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Tue Aug 16 12:14:44 2016
@@ -550,8 +550,8 @@ void HexagonAsmPrinter::HexagonProcessIn
Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
return;
}
- case Hexagon::HEXAGON_V6_vd0_pseudo:
- case Hexagon::HEXAGON_V6_vd0_pseudo_128B: {
+ case Hexagon::V6_vd0:
+ case Hexagon::V6_vd0_128B: {
MCInst TmpInst;
assert (Inst.getOperand(0).isReg() &&
"Expected register and none was found");
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td?rev=278823&r1=278822&r2=278823&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td Tue Aug 16 12:14:44 2016
@@ -492,12 +492,10 @@ def : InstAlias<"if ($src1) jumpr $src2"
def : InstAlias<"if (!$src1) jumpr $src2",
(J2_jumprf PredRegs:$src1, IntRegs:$src2), 0>;
-// V6_vassignp: Vector assign mapping.
-let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
-def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
- (outs VecDblRegs:$Vdd),
- (ins VecDblRegs:$Vss),
- "$Vdd = $Vss">;
+// maps Vdd = Vss to Vdd = V6_vassignp(Vss)
+def : InstAlias<"$Vdd = $Vss",
+ (V6_vassignp VecDblRegs:$Vdd, VecDblRegs:$Vss)>,
+ Requires<[HasV60T]>;
// maps Vd = #0 to Vd = vxor(Vd, Vd)
def : InstAlias<"$Vd = #0",
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=278823&r1=278822&r2=278823&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Aug 16 12:14:44 2016
@@ -1013,17 +1013,19 @@ bool HexagonInstrInfo::expandPostRAPseud
.addImm(-MI.getOperand(1).getImm());
MBB.erase(MI);
return true;
- case Hexagon::HEXAGON_V6_vassignp_128B:
- case Hexagon::HEXAGON_V6_vassignp: {
+ case Hexagon::V6_vassignp_128B:
+ case Hexagon::V6_vassignp: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
- if (SrcReg != DstReg)
- copyPhysReg(MBB, MI, DL, DstReg, SrcReg, MI.getOperand(1).isKill());
+ unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
+ BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
+ .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), Kill)
+ .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), Kill);
MBB.erase(MI);
return true;
}
- case Hexagon::HEXAGON_V6_lo_128B:
- case Hexagon::HEXAGON_V6_lo: {
+ case Hexagon::V6_lo_128B:
+ case Hexagon::V6_lo: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
@@ -1032,8 +1034,8 @@ bool HexagonInstrInfo::expandPostRAPseud
MRI.clearKillFlags(SrcSubLo);
return true;
}
- case Hexagon::HEXAGON_V6_hi_128B:
- case Hexagon::HEXAGON_V6_hi: {
+ case Hexagon::V6_hi_128B:
+ case Hexagon::V6_hi: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td?rev=278823&r1=278822&r2=278823&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td Tue Aug 16 12:14:44 2016
@@ -2263,3 +2263,25 @@ def V6_vhistq
def V6_vhist
: CVI_HIST_Resource1 <(outs), (ins),
"vhist" >, V6_vhist_enc;
+
+
+let isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
+ def V6_vd0: CVI_VA_Resource<(outs VectorRegs:$dst), (ins), "$dst = #0", []>;
+ def V6_vd0_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), (ins),
+ "$dst = #0", []>;
+
+ def V6_vassignp: CVI_VA_Resource<(outs VecDblRegs:$dst),
+ (ins VecDblRegs:$src), "", []>;
+ def V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst),
+ (ins VecDblRegs128B:$src), "", []>;
+
+ def V6_lo: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1),
+ "", []>;
+ def V6_lo_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst),
+ (ins VecDblRegs128B:$src1), "", []>;
+
+ def V6_hi: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1),
+ "", []>;
+ def V6_hi_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst),
+ (ins VecDblRegs128B:$src1), "", []>;
+}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td?rev=278823&r1=278822&r2=278823&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td Tue Aug 16 12:14:44 2016
@@ -12,55 +12,6 @@
//===----------------------------------------------------------------------===//
-let isCodeGenOnly = 1 in {
-def HEXAGON_V6_vd0_pseudo : CVI_VA_Resource<(outs VectorRegs:$dst),
- (ins ),
- "$dst=#0",
- [(set VectorRegs:$dst, (int_hexagon_V6_vd0 ))]>;
-
-def HEXAGON_V6_vd0_pseudo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst),
- (ins ),
- "$dst=#0",
- [(set VectorRegs128B:$dst, (int_hexagon_V6_vd0_128B ))]>;
-}
-
-let isPseudo = 1 in
-def HEXAGON_V6_vassignp : CVI_VA_Resource<(outs VecDblRegs:$dst),
- (ins VecDblRegs:$src1),
- "$dst=vassignp_W($src1)",
- [(set VecDblRegs:$dst, (int_hexagon_V6_vassignp VecDblRegs:$src1))]>;
-
-let isPseudo = 1 in
-def HEXAGON_V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst),
- (ins VecDblRegs128B:$src1),
- "$dst=vassignp_W_128B($src1)",
- [(set VecDblRegs128B:$dst, (int_hexagon_V6_vassignp_128B
- VecDblRegs128B:$src1))]>;
-
-let isPseudo = 1 in
-def HEXAGON_V6_lo : CVI_VA_Resource<(outs VectorRegs:$dst),
- (ins VecDblRegs:$src1),
- "$dst=lo_W($src1)",
- [(set VectorRegs:$dst, (int_hexagon_V6_lo VecDblRegs:$src1))]>;
-
-let isPseudo = 1 in
-def HEXAGON_V6_hi : CVI_VA_Resource<(outs VectorRegs:$dst),
- (ins VecDblRegs:$src1),
- "$dst=hi_W($src1)",
- [(set VectorRegs:$dst, (int_hexagon_V6_hi VecDblRegs:$src1))]>;
-
-let isPseudo = 1 in
-def HEXAGON_V6_lo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst),
- (ins VecDblRegs128B:$src1),
- "$dst=lo_W($src1)",
- [(set VectorRegs128B:$dst, (int_hexagon_V6_lo_128B VecDblRegs128B:$src1))]>;
-
-let isPseudo = 1 in
-def HEXAGON_V6_hi_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst),
- (ins VecDblRegs128B:$src1),
- "$dst=hi_W($src1)",
- [(set VectorRegs128B:$dst, (int_hexagon_V6_hi_128B VecDblRegs128B:$src1))]>;
-
let AddedComplexity = 100 in {
def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
(v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
@@ -204,6 +155,16 @@ multiclass T_V_pat <InstHexagon MI, Intr
Requires<[UseHVXDbl]>;
}
+multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
+ def: Pat<(IntID VecDblRegs:$src1),
+ (MI VecDblRegs:$src1)>,
+ Requires<[UseHVXSgl]>;
+
+ def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1),
+ (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1)>,
+ Requires<[UseHVXDbl]>;
+}
+
multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
def: Pat<(IntID VecPredRegs:$src1),
(MI VecPredRegs:$src1)>,
@@ -495,7 +456,7 @@ multiclass T_WVVR_pat <InstHexagon MI, I
Requires<[UseHVXDbl]>;
}
-defm : T_WR_pat<V6_vtmpyb, int_hexagon_V6_vtmpyb>;
+defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>;
defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>;
defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>;
defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>;
@@ -751,6 +712,10 @@ defm : T_V_pat <V6_vcl0h, int_hexagon_V6
defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>;
defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>;
+defm : T_W_pat <V6_lo, int_hexagon_V6_lo>;
+defm : T_W_pat <V6_hi, int_hexagon_V6_hi>;
+defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>;
+
defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>;
defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>;
defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>;
@@ -831,8 +796,10 @@ def : T_PPQ_pat <S2_cabacencbin, int_hex
def: Pat<(v64i16 (trunc v64i32:$Vdd)),
(v64i16 (V6_vpackwh_sat_128B
- (v32i32 (HEXAGON_V6_hi_128B VecDblRegs128B:$Vdd)),
- (v32i32 (HEXAGON_V6_lo_128B VecDblRegs128B:$Vdd))))>,
+ (v32i32 (V6_hi_128B VecDblRegs128B:$Vdd)),
+ (v32i32 (V6_lo_128B VecDblRegs128B:$Vdd))))>,
Requires<[UseHVXDbl]>;
+def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>;
+def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0_128B)>;
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