[PATCH] D23547: [mips] Enforce compact branch restrictions

[Simon Dardis via llvm-commits]

sdardis created this revision.
sdardis added reviewers: dsanders, vkalintiris.
sdardis added a subscriber: llvm-commits.
Herald added a subscriber: sdardis.

Check both operands for use of the $zero register which cannot be used with
an compact branch instruction.

https://reviews.llvm.org/D23547

Files:
  lib/Target/Mips/MipsInstrInfo.cpp
  test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll

Index: test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
===================================================================
--- test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
+++ test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
@@ -100,3 +100,33 @@
   if.end:
     ret i64 0
 }
+
+define i32 @f6(i32 %a) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: beqc ${{[0-9]+}}, $zero, $BB[0-9]+_[0-9]+
+; CHECK-NOT: bnec ${{[0-9]+}}, $zero, $BB[0-9]+_[0-9]+
+
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
+
+define i32 @f7(i32 %a) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: beqc $zero, ${{[0-9]+}}, $BB[0-9]+_[0-9]+
+; CHECK-NOT: bnec $zero, ${{[0-9]+}}, $BB[0-9]+_[0-9]+
+
+  %cmp = icmp eq i32 0, %a
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
Index: lib/Target/Mips/MipsInstrInfo.cpp
===================================================================
--- lib/Target/Mips/MipsInstrInfo.cpp
+++ lib/Target/Mips/MipsInstrInfo.cpp
@@ -430,10 +430,16 @@
   // Mips::ZERO, which is incorrect. This test should be updated to use
   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
   // are fixed.
+  unsigned ZeroOperandPosition = 0;
   bool BranchWithZeroOperand =
-      (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() &&
-       (I->getOperand(1).getReg() == Mips::ZERO ||
-        I->getOperand(1).getReg() == Mips::ZERO_64));
+      I->isBranch() && !I->isPseudo() &&
+      (I->readsRegister(Mips::ZERO) || I->readsRegister(Mips::ZERO_64));
+  if (BranchWithZeroOperand) {
+    ZeroOperandPosition =
+        I->findRegisterUseOperandIdx(Mips::ZERO) == -1
+            ? (unsigned)I->findRegisterUseOperandIdx(Mips::ZERO_64)
+            : (unsigned)I->findRegisterUseOperandIdx(Mips::ZERO);
+  }
 
   if (BranchWithZeroOperand) {
     switch (NewOpc) {
@@ -476,17 +482,14 @@
 
     MIB.addImm(0);
 
- } else if (BranchWithZeroOperand) {
-    // For MIPSR6 and microMIPS branches with an explicit zero operand, copy
-    // everything after the zero.
-     MIB.addOperand(I->getOperand(0));
+ } else {
 
-    for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) {
-      MIB.addOperand(I->getOperand(J));
-    }
-  } else {
-    // All other cases copy all other operands.
+    // For MIPSR6 and microMIPS branches with an explicit zero operand, skip
+    // copying the zero.
     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
+      if (BranchWithZeroOperand && ZeroOperandPosition == J)
+        continue;
+
       MIB.addOperand(I->getOperand(J));
     }
   }


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