[llvm] r278588 - AMDGPU/R600: Remove macros
Reid Kleckner via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 15 17:04:13 PDT 2016
This caused test failures with MSVC 2013:
http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9730
MSVC didn't make your enum 64-bits, so it truncated most of the interesting
bits of the values. Fixed in r278762.
On Fri, Aug 12, 2016 at 6:43 PM, Matt Arsenault via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: arsenm
> Date: Fri Aug 12 20:43:46 2016
> New Revision: 278588
>
> URL: http://llvm.org/viewvc/llvm-project?rev=278588&view=rev
> Log:
> AMDGPU/R600: Remove macros
>
> Modified:
> llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
> llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
> llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> AMDGPU/AMDGPUInstrInfo.h?rev=278588&r1=278587&r2=278588&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h Fri Aug 12 20:43:46
> 2016
> @@ -23,11 +23,6 @@
> #define GET_INSTRINFO_OPERAND_ENUM
> #include "AMDGPUGenInstrInfo.inc"
>
> -#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
> -#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
> -#define OPCODE_IS_ZERO AMDGPU::PRED_SETE
> -#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
> -
> namespace llvm {
>
> class AMDGPUSubtarget;
> @@ -67,7 +62,4 @@ namespace AMDGPU {
>
> } // End llvm namespace
>
> -#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
> -#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
> -
> #endif
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> AMDGPU/AMDILCFGStructurizer.cpp?rev=278588&r1=278587&r2=278588&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp Fri Aug 12
> 20:43:46 2016
> @@ -430,17 +430,17 @@ void AMDGPUCFGStructurizer::reversePredi
> continue;
> if (I->getOpcode() == AMDGPU::PRED_X) {
> switch (I->getOperand(2).getImm()) {
> - case OPCODE_IS_ZERO_INT:
> - I->getOperand(2).setImm(OPCODE_IS_NOT_ZERO_INT);
> + case AMDGPU::PRED_SETE_INT:
> + I->getOperand(2).setImm(AMDGPU::PRED_SETNE_INT);
> return;
> - case OPCODE_IS_NOT_ZERO_INT:
> - I->getOperand(2).setImm(OPCODE_IS_ZERO_INT);
> + case AMDGPU::PRED_SETNE_INT:
> + I->getOperand(2).setImm(AMDGPU::PRED_SETE_INT);
> return;
> - case OPCODE_IS_ZERO:
> - I->getOperand(2).setImm(OPCODE_IS_NOT_ZERO);
> + case AMDGPU::PRED_SETE:
> + I->getOperand(2).setImm(AMDGPU::PRED_SETNE);
> return;
> - case OPCODE_IS_NOT_ZERO:
> - I->getOperand(2).setImm(OPCODE_IS_ZERO);
> + case AMDGPU::PRED_SETNE:
> + I->getOperand(2).setImm(AMDGPU::PRED_SETE);
> return;
> default:
> llvm_unreachable("PRED_X Opcode invalid!");
>
> Modified: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> AMDGPU/R600ISelLowering.cpp?rev=278588&r1=278587&r2=278588&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp Fri Aug 12 20:43:46
> 2016
> @@ -328,7 +328,7 @@ R600TargetLowering::EmitInstrWithCustomI
> BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
> AMDGPU::PREDICATE_BIT)
> .addOperand(MI.getOperand(1))
> - .addImm(OPCODE_IS_NOT_ZERO)
> + .addImm(AMDGPU::PRED_SETNE)
> .addImm(0); // Flags
> TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
> BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
> @@ -342,7 +342,7 @@ R600TargetLowering::EmitInstrWithCustomI
> BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
> AMDGPU::PREDICATE_BIT)
> .addOperand(MI.getOperand(1))
> - .addImm(OPCODE_IS_NOT_ZERO_INT)
> + .addImm(AMDGPU::PRED_SETNE_INT)
> .addImm(0); // Flags
> TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
> BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
>
> Modified: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> AMDGPU/R600InstrInfo.cpp?rev=278588&r1=278587&r2=278588&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp Fri Aug 12 20:43:46
> 2016
> @@ -910,17 +910,17 @@ bool
> R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand>
> &Cond) const {
> MachineOperand &MO = Cond[1];
> switch (MO.getImm()) {
> - case OPCODE_IS_ZERO_INT:
> - MO.setImm(OPCODE_IS_NOT_ZERO_INT);
> + case AMDGPU::PRED_SETE_INT:
> + MO.setImm(AMDGPU::PRED_SETNE_INT);
> break;
> - case OPCODE_IS_NOT_ZERO_INT:
> - MO.setImm(OPCODE_IS_ZERO_INT);
> + case AMDGPU::PRED_SETNE_INT:
> + MO.setImm(AMDGPU::PRED_SETE_INT);
> break;
> - case OPCODE_IS_ZERO:
> - MO.setImm(OPCODE_IS_NOT_ZERO);
> + case AMDGPU::PRED_SETE:
> + MO.setImm(AMDGPU::PRED_SETNE);
> break;
> - case OPCODE_IS_NOT_ZERO:
> - MO.setImm(OPCODE_IS_ZERO);
> + case AMDGPU::PRED_SETNE:
> + MO.setImm(AMDGPU::PRED_SETE);
> break;
> default:
> return true;
> @@ -1478,11 +1478,3 @@ void R600InstrInfo::clearFlag(MachineIns
> FlagOp.setImm(InstFlags);
> }
> }
> -
> -bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
> - return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
> -}
> -
> -bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
> - return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
> -}
>
> Modified: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> AMDGPU/R600InstrInfo.h?rev=278588&r1=278587&r2=278588&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h Fri Aug 12 20:43:46 2016
> @@ -19,6 +19,14 @@
> #include "R600RegisterInfo.h"
>
> namespace llvm {
> +
> +namespace R600InstrFlags {
> +enum {
> + REGISTER_STORE = UINT64_C(1) << 62,
> + REGISTER_LOAD = UINT64_C(1) << 63
> +};
> +}
> +
> class AMDGPUTargetMachine;
> class DFAPacketizer;
> class MachineFunction;
> @@ -301,8 +309,13 @@ public:
> void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
>
> // Helper functions that check the opcode for status information
> - bool isRegisterStore(const MachineInstr &MI) const;
> - bool isRegisterLoad(const MachineInstr &MI) const;
> + bool isRegisterStore(const MachineInstr &MI) const {
> + return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
> + }
> +
> + bool isRegisterLoad(const MachineInstr &MI) const {
> + return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
> + }
> };
>
> namespace AMDGPU {
>
>
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