<div dir="ltr">This caused test failures with MSVC 2013:<div><a href="http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9730">http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9730</a><br></div><div><br></div><div>MSVC didn't make your enum 64-bits, so it truncated most of the interesting bits of the values. Fixed in r278762.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Aug 12, 2016 at 6:43 PM, Matt Arsenault via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: arsenm<br>
Date: Fri Aug 12 20:43:46 2016<br>
New Revision: 278588<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=278588&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=278588&view=rev</a><br>
Log:<br>
AMDGPU/R600: Remove macros<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUInstrInfo.h<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>AMDILCFGStructurizer.cpp<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>R600ISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.h<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUInstrInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h?rev=278588&r1=278587&r2=278588&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/AMDGPUInstrInfo.h?rev=<wbr>278588&r1=278587&r2=278588&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUInstrInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUInstrInfo.h Fri Aug 12 20:43:46 2016<br>
@@ -23,11 +23,6 @@<br>
#define GET_INSTRINFO_OPERAND_ENUM<br>
#include "AMDGPUGenInstrInfo.inc"<br>
<br>
-#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT<br>
-#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT<br>
-#define OPCODE_IS_ZERO AMDGPU::PRED_SETE<br>
-#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE<br>
-<br>
namespace llvm {<br>
<br>
class AMDGPUSubtarget;<br>
@@ -67,7 +62,4 @@ namespace AMDGPU {<br>
<br>
} // End llvm namespace<br>
<br>
-#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)<br>
-#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)<br>
-<br>
#endif<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>AMDILCFGStructurizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp?rev=278588&r1=278587&r2=278588&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/AMDILCFGStructurizer.<wbr>cpp?rev=278588&r1=278587&r2=<wbr>278588&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>AMDILCFGStructurizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>AMDILCFGStructurizer.cpp Fri Aug 12 20:43:46 2016<br>
@@ -430,17 +430,17 @@ void AMDGPUCFGStructurizer::<wbr>reversePredi<br>
continue;<br>
if (I->getOpcode() == AMDGPU::PRED_X) {<br>
switch (I->getOperand(2).getImm()) {<br>
- case OPCODE_IS_ZERO_INT:<br>
- I->getOperand(2).setImm(<wbr>OPCODE_IS_NOT_ZERO_INT);<br>
+ case AMDGPU::PRED_SETE_INT:<br>
+ I->getOperand(2).setImm(<wbr>AMDGPU::PRED_SETNE_INT);<br>
return;<br>
- case OPCODE_IS_NOT_ZERO_INT:<br>
- I->getOperand(2).setImm(<wbr>OPCODE_IS_ZERO_INT);<br>
+ case AMDGPU::PRED_SETNE_INT:<br>
+ I->getOperand(2).setImm(<wbr>AMDGPU::PRED_SETE_INT);<br>
return;<br>
- case OPCODE_IS_ZERO:<br>
- I->getOperand(2).setImm(<wbr>OPCODE_IS_NOT_ZERO);<br>
+ case AMDGPU::PRED_SETE:<br>
+ I->getOperand(2).setImm(<wbr>AMDGPU::PRED_SETNE);<br>
return;<br>
- case OPCODE_IS_NOT_ZERO:<br>
- I->getOperand(2).setImm(<wbr>OPCODE_IS_ZERO);<br>
+ case AMDGPU::PRED_SETNE:<br>
+ I->getOperand(2).setImm(<wbr>AMDGPU::PRED_SETE);<br>
return;<br>
default:<br>
llvm_unreachable("PRED_X Opcode invalid!");<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>R600ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=278588&r1=278587&r2=278588&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/R600ISelLowering.cpp?<wbr>rev=278588&r1=278587&r2=<wbr>278588&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>R600ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>R600ISelLowering.cpp Fri Aug 12 20:43:46 2016<br>
@@ -328,7 +328,7 @@ R600TargetLowering::<wbr>EmitInstrWithCustomI<br>
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),<br>
AMDGPU::PREDICATE_BIT)<br>
.addOperand(MI.getOperand(1))<br>
- .addImm(OPCODE_IS_NOT_ZERO)<br>
+ .addImm(AMDGPU::PRED_SETNE)<br>
.addImm(0); // Flags<br>
TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);<br>
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))<br>
@@ -342,7 +342,7 @@ R600TargetLowering::<wbr>EmitInstrWithCustomI<br>
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),<br>
AMDGPU::PREDICATE_BIT)<br>
.addOperand(MI.getOperand(1))<br>
- .addImm(OPCODE_IS_NOT_ZERO_<wbr>INT)<br>
+ .addImm(AMDGPU::PRED_SETNE_<wbr>INT)<br>
.addImm(0); // Flags<br>
TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);<br>
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp?rev=278588&r1=278587&r2=278588&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/R600InstrInfo.cpp?rev=<wbr>278588&r1=278587&r2=278588&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.cpp Fri Aug 12 20:43:46 2016<br>
@@ -910,17 +910,17 @@ bool<br>
R600InstrInfo::<wbr>ReverseBranchCondition(<wbr>SmallVectorImpl<<wbr>MachineOperand> &Cond) const {<br>
MachineOperand &MO = Cond[1];<br>
switch (MO.getImm()) {<br>
- case OPCODE_IS_ZERO_INT:<br>
- MO.setImm(OPCODE_IS_NOT_ZERO_<wbr>INT);<br>
+ case AMDGPU::PRED_SETE_INT:<br>
+ MO.setImm(AMDGPU::PRED_SETNE_<wbr>INT);<br>
break;<br>
- case OPCODE_IS_NOT_ZERO_INT:<br>
- MO.setImm(OPCODE_IS_ZERO_INT);<br>
+ case AMDGPU::PRED_SETNE_INT:<br>
+ MO.setImm(AMDGPU::PRED_SETE_<wbr>INT);<br>
break;<br>
- case OPCODE_IS_ZERO:<br>
- MO.setImm(OPCODE_IS_NOT_ZERO);<br>
+ case AMDGPU::PRED_SETE:<br>
+ MO.setImm(AMDGPU::PRED_SETNE);<br>
break;<br>
- case OPCODE_IS_NOT_ZERO:<br>
- MO.setImm(OPCODE_IS_ZERO);<br>
+ case AMDGPU::PRED_SETNE:<br>
+ MO.setImm(AMDGPU::PRED_SETE);<br>
break;<br>
default:<br>
return true;<br>
@@ -1478,11 +1478,3 @@ void R600InstrInfo::clearFlag(<wbr>MachineIns<br>
FlagOp.setImm(InstFlags);<br>
}<br>
}<br>
-<br>
-bool R600InstrInfo::<wbr>isRegisterStore(const MachineInstr &MI) const {<br>
- return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;<br>
-}<br>
-<br>
-bool R600InstrInfo::isRegisterLoad(<wbr>const MachineInstr &MI) const {<br>
- return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;<br>
-}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h?rev=278588&r1=278587&r2=278588&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/R600InstrInfo.h?rev=<wbr>278588&r1=278587&r2=278588&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>R600InstrInfo.h Fri Aug 12 20:43:46 2016<br>
@@ -19,6 +19,14 @@<br>
#include "R600RegisterInfo.h"<br>
<br>
namespace llvm {<br>
+<br>
+namespace R600InstrFlags {<br>
+enum {<br>
+ REGISTER_STORE = UINT64_C(1) << 62,<br>
+ REGISTER_LOAD = UINT64_C(1) << 63<br>
+};<br>
+}<br>
+<br>
class AMDGPUTargetMachine;<br>
class DFAPacketizer;<br>
class MachineFunction;<br>
@@ -301,8 +309,13 @@ public:<br>
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;<br>
<br>
// Helper functions that check the opcode for status information<br>
- bool isRegisterStore(const MachineInstr &MI) const;<br>
- bool isRegisterLoad(const MachineInstr &MI) const;<br>
+ bool isRegisterStore(const MachineInstr &MI) const {<br>
+ return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_<wbr>STORE;<br>
+ }<br>
+<br>
+ bool isRegisterLoad(const MachineInstr &MI) const {<br>
+ return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;<br>
+ }<br>
};<br>
<br>
namespace AMDGPU {<br>
<br>
<br>
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</blockquote></div><br></div>