[PATCH] D23207: If-conversion incorrectly calculates liveness of redefined registers

[Krzysztof Parzyszek via llvm-commits]

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The if-convert-diamond function in the if-conversion initialized Redefs with the live-ins from the first of the two predicated blocks.  This may not reflect the liveness of the defined registers correctly, since a register defined in the first block may be live across the other predicated block.  The testcase illustrates this situation.

Repository:
  rL LLVM

https://reviews.llvm.org/D23207

Files:
  lib/CodeGen/IfConversion.cpp
  test/CodeGen/Hexagon/ifcvt-impuse-livein.mir

Index: test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
===================================================================
--- /dev/null
+++ test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
@@ -0,0 +1,34 @@
+# RUN: llc -march=hexagon -run-pass if-converter %s -o - | FileCheck %s
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+---
+name: foo
+tracksRegLiveness: true
+allVRegsAllocated: true
+body: |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %r0, %r1, %r2, %p1
+        J2_jumpf %p1, %bb.1, implicit-def %pc
+        J2_jump %bb.2, implicit-def %pc
+  bb.1:
+    successors: %bb.3
+    liveins: %r2
+        %r0 = A2_tfrsi 2
+        J2_jump %bb.3, implicit-def %pc
+  bb.2:
+    successors: %bb.3
+    liveins: %r0
+    ; CHECK: %r2 = C2_cmoveit %p1, 1, implicit %r2
+        %r2 = A2_tfrsi 1
+  bb.3:
+    liveins: %r0, %r2
+        %r0 = A2_add %r0, %r2
+        J2_jumpr %r31, implicit-def %pc
+...
+
Index: lib/CodeGen/IfConversion.cpp
===================================================================
--- lib/CodeGen/IfConversion.cpp
+++ lib/CodeGen/IfConversion.cpp
@@ -1078,6 +1078,7 @@
   // Before stepping forward past MI, remember which regs were live
   // before MI. This is needed to set the Undef flag only when reg is
   // dead.
+dbgs() << __func__ << "  Redefs:" << Redefs << "  MI:" << MI;
   SparseSet<unsigned> LiveBeforeMI;
   LiveBeforeMI.setUniverse(TRI->getNumRegs());
   for (auto &Reg : Redefs)
@@ -1431,10 +1432,11 @@
   // Remove the conditional branch from entry to the blocks.
   BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
 
-  // Initialize liveins to the first BB. These are potentially redefined by
-  // predicated instructions.
+  // Initialize Redefs to be the live-outs from the split block. These are
+  // potentially redefined by predicated instructions.
   Redefs.init(TRI);
   Redefs.addLiveIns(*BBI1->BB);
+  Redefs.addLiveIns(*BBI2->BB);
 
   // Remove the duplicated instructions at the beginnings of both paths.
   // Skip dbg_value instructions


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