[llvm] r277483 - [GlobalISel] Verify Selected MF property.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Tue Aug  2 11:49:22 2016
New Revision: 277483

URL: http://llvm.org/viewvc/llvm-project?rev=277483&view=rev
Log:
[GlobalISel] Verify Selected MF property.

After instruction selection, there should be no pre-isel generic
instructions remaining, nor should generic virtual registers be
used. Verify that.

Added:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=277483&r1=277482&r2=277483&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Aug  2 11:49:22 2016
@@ -72,6 +72,7 @@ namespace {
 
     // Avoid querying the MachineFunctionProperties for each operand.
     bool isFunctionRegBankSelected;
+    bool isFunctionSelected;
 
     typedef SmallVector<unsigned, 16> RegVector;
     typedef SmallVector<const uint32_t*, 4> RegMaskVector;
@@ -335,6 +336,8 @@ unsigned MachineVerifier::verify(Machine
 
   isFunctionRegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
+  isFunctionSelected = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::Selected);
 
   LiveVars = nullptr;
   LiveInts = nullptr;
@@ -887,6 +890,9 @@ void MachineVerifier::visitMachineInstrB
   // Check types.
   const unsigned NumTypes = MI->getNumTypes();
   if (isPreISelGenericOpcode(MCID.getOpcode())) {
+    if (isFunctionSelected)
+      report("Unexpected generic instruction in a Selected function", MI);
+
     if (NumTypes == 0)
       report("Generic instruction must have a type", MI);
   } else {
@@ -1003,7 +1009,15 @@ MachineVerifier::visitMachineOperand(con
         const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
         if (!RC) {
           // This is a generic virtual register.
-          // It must have a size and it must not have a SubIdx.
+
+          // If we're post-Select, we can't have gvregs anymore.
+          if (isFunctionSelected) {
+            report("Generic virtual register invalid in a Selected function",
+                   MO, MONum);
+            return;
+          }
+
+          // The gvreg must have a size and it must not have a SubIdx.
           unsigned Size = MRI->getSize(Reg);
           if (!Size) {
             report("Generic virtual register must have a size", MO, MONum);

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir?rev=277483&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir Tue Aug  2 11:49:22 2016
@@ -0,0 +1,31 @@
+# RUN: not llc -mtriple aarch64-- -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define void @test() { ret void }
+
+...
+
+---
+name:            test
+isSSA: true
+regBankSelected: true
+selected: true
+registers:
+  - { id: 0, class: gpr64 }
+  - { id: 1, class: gpr64 }
+  - { id: 2, class: gpr }
+body: |
+  bb.0:
+   liveins: %x0
+   %0 = COPY %x0
+
+   ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
+   ; CHECK: instruction: %vreg1<def> = G_ADD { s32 }
+   %1 = G_ADD s32 %0, %0
+
+   ; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function ***
+   ; CHECK: instruction: %vreg2<def>(64) = COPY
+   ; CHECK: operand 0: %vreg2<def>
+   %2(64) = COPY %x0
+...