[llvm] r277482 - [GlobalISel] Add Selected MachineFunction property.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 2 09:49:19 PDT 2016
Author: ab
Date: Tue Aug 2 11:49:19 2016
New Revision: 277482
URL: http://llvm.org/viewvc/llvm-project?rev=277482&view=rev
Log:
[GlobalISel] Add Selected MachineFunction property.
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).
Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/include/llvm/CodeGen/MachineFunction.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=277482&r1=277481&r2=277482&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Tue Aug 2 11:49:19 2016
@@ -387,6 +387,7 @@ struct MachineFunction {
// GISel MachineFunctionProperties.
bool Legalized = false;
bool RegBankSelected = false;
+ bool Selected = false;
// Register information
bool IsSSA = false;
bool TracksRegLiveness = false;
@@ -413,6 +414,7 @@ template <> struct MappingTraits<Machine
YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
+ YamlIO.mapOptional("selected", MF.Selected);
YamlIO.mapOptional("isSSA", MF.IsSSA);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=277482&r1=277481&r2=277482&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Aug 2 11:49:19 2016
@@ -124,12 +124,20 @@ public:
// - legal pre-isel generic instructions.
// RegBankSelected: In GlobalISel: the RegBankSelect pass ran and all generic
// virtual registers have been assigned to a register bank.
+ // Selected: In GlobalISel: the InstructionSelect pass ran and all pre-isel
+ // generic instructions have been eliminated; i.e., all instructions are now
+ // target-specific or non-pre-isel generic instructions (e.g., COPY).
+ // Since only pre-isel generic instructions can have generic virtual register
+ // operands, this also means that all generic virtual registers have been
+ // constrained to virtual registers (assigned to register classes) and that
+ // all sizes attached to them have been eliminated.
enum class Property : unsigned {
IsSSA,
TracksLiveness,
AllVRegsAllocated,
Legalized,
RegBankSelected,
+ Selected,
LastProperty,
};
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=277482&r1=277481&r2=277482&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug 2 11:49:19 2016
@@ -298,6 +298,8 @@ bool MIRParserImpl::initializeMachineFun
if (YamlMF.RegBankSelected)
MF.getProperties().set(
MachineFunctionProperties::Property::RegBankSelected);
+ if (YamlMF.Selected)
+ MF.getProperties().set(MachineFunctionProperties::Property::Selected);
PerFunctionMIParsingState PFS(MF, SM, IRSlots);
if (initializeRegisterInfo(PFS, YamlMF))
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=277482&r1=277481&r2=277482&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Aug 2 11:49:19 2016
@@ -182,6 +182,8 @@ void MIRPrinter::print(const MachineFunc
MachineFunctionProperties::Property::Legalized);
YamlMF.RegBankSelected = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::RegBankSelected);
+ YamlMF.Selected = MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::Selected);
convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
ModuleSlotTracker MST(MF.getFunction()->getParent());
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=277482&r1=277481&r2=277482&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Aug 2 11:49:19 2016
@@ -82,6 +82,9 @@ void MachineFunctionProperties::print(ra
case Property::RegBankSelected:
ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
break;
+ case Property::Selected:
+ ROS << (HasProperty ? "" : "not ") << "selected";
+ break;
default:
break;
}
Modified: llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir?rev=277482&r1=277481&r2=277482&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir Tue Aug 2 11:49:19 2016
@@ -21,6 +21,7 @@
# CHECK-LABEL: name: test_defaults
# CHECK: legalized: false
# CHECK-NEXT: regBankSelected: false
+# CHECK-NEXT: selected: false
name: test_defaults
body: |
bb.0:
@@ -29,9 +30,11 @@ body: |
# CHECK-LABEL: name: test
# CHECK: legalized: true
# CHECK-NEXT: regBankSelected: true
+# CHECK-NEXT: selected: true
name: test
legalized: true
regBankSelected: true
+selected: true
body: |
bb.0:
...
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