[llvm] r277144 - Add missing files to r277143
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 06:59:55 PDT 2016
Author: kparzysz
Date: Fri Jul 29 08:59:55 2016
New Revision: 277144
URL: http://llvm.org/viewvc/llvm-project?rev=277144&view=rev
Log:
Add missing files to r277143
Added:
llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h
Added: llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp?rev=277144&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp Fri Jul 29 08:59:55 2016
@@ -0,0 +1,138 @@
+//===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the hazard recognizer for scheduling on Hexagon.
+// Use a DFA based hazard recognizer.
+//
+//===----------------------------------------------------------------------===//
+
+#include "HexagonHazardRecognizer.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "post-RA-sched"
+
+void HexagonHazardRecognizer::Reset() {
+ DEBUG(dbgs() << "Reset hazard recognizer\n");
+ Resources->clearResources();
+ PacketNum = 0;
+ UsesDotCur = nullptr;
+ DotCurPNum = -1;
+ RegDefs.clear();
+}
+
+ScheduleHazardRecognizer::HazardType
+HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) {
+ MachineInstr *MI = SU->getInstr();
+ if (!MI || TII->isZeroCost(MI->getOpcode()))
+ return NoHazard;
+
+ if (!Resources->canReserveResources(*MI)) {
+ DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
+ HazardType RetVal = Hazard;
+ if (TII->mayBeNewStore(MI)) {
+ // Make sure the register to be stored is defined by an instruction in the
+ // packet.
+ MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
+ if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
+ return Hazard;
+ // The .new store version uses different resources so check if it
+ // causes a hazard.
+ MachineFunction *MF = MI->getParent()->getParent();
+ MachineInstr *NewMI =
+ MF->CreateMachineInstr(TII->get(TII->getDotNewOp(MI)),
+ MI->getDebugLoc());
+ if (Resources->canReserveResources(*NewMI))
+ RetVal = NoHazard;
+ DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) << "\n");
+ MF->DeleteMachineInstr(NewMI);
+ }
+ return RetVal;
+ }
+
+ if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {
+ DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " << *MI);
+ return Hazard;
+ }
+
+ return NoHazard;
+}
+
+void HexagonHazardRecognizer::AdvanceCycle() {
+ DEBUG(dbgs() << "Advance cycle, clear state\n");
+ Resources->clearResources();
+ if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) {
+ UsesDotCur = nullptr;
+ DotCurPNum = -1;
+ }
+ PacketNum++;
+ RegDefs.clear();
+}
+
+/// If a packet contains a dot cur instruction, then we may prefer the
+/// instruction that can use the dot cur result. Or, if the use
+/// isn't scheduled in the same packet, then prefer other instructions
+/// in the subsequent packet.
+bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
+ return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));
+}
+
+void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {
+ MachineInstr *MI = SU->getInstr();
+ if (!MI)
+ return;
+
+ // Keep the set of definitions for each packet, which is used to determine
+ // if a .new can be used.
+ for (ConstMIOperands MO(*MI); MO.isValid(); ++MO)
+ if (MO->isReg() && MO->isDef() && !MO->isImplicit())
+ RegDefs.insert(MO->getReg());
+
+ if (TII->isZeroCost(MI->getOpcode()))
+ return;
+
+ if (!Resources->canReserveResources(*MI)) {
+ // It must be a .new store since other instructions must be able to be
+ // reserved at this point.
+ assert(TII->mayBeNewStore(MI) && "Expecting .new store");
+ MachineFunction *MF = MI->getParent()->getParent();
+ MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(TII->getDotNewOp(MI)),
+ MI->getDebugLoc());
+ assert(Resources->canReserveResources(*NewMI));
+ Resources->reserveResources(*NewMI);
+ MF->DeleteMachineInstr(NewMI);
+ }
+ else
+ Resources->reserveResources(*MI);
+ DEBUG(dbgs() << " Add instruction " << *MI);
+
+ // When scheduling a dot cur instruction, check if there is an instruction
+ // that can use the dot cur in the same packet. If so, we'll attempt to
+ // schedule it before other instructions. We only do this if the use has
+ // the same height as the dot cur. Otherwise, we may miss scheduling an
+ // instruction with a greater height, which is more important.
+ if (TII->mayBeCurLoad(MI))
+ for (auto &S : SU->Succs)
+ if (S.isAssignedRegDep() && S.getLatency() == 0 &&
+ SU->getHeight() == S.getSUnit()->getHeight()) {
+ UsesDotCur = S.getSUnit();
+ DotCurPNum = PacketNum;
+ break;
+ }
+ if (SU == UsesDotCur) {
+ UsesDotCur = nullptr;
+ DotCurPNum = -1;
+ }
+}
Added: llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h?rev=277144&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h Fri Jul 29 08:59:55 2016
@@ -0,0 +1,75 @@
+//===--- HexagonHazardRecognizer.h - Hexagon Post RA Hazard Recognizer ----===//
+//
+// (c) 2014 Qualcomm Innovation Center, Inc. All rights reserved.
+//
+// This file defines the hazard recognizer for scheduling on Hexagon.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef HEXAGONPROFITRECOGNIZER_H
+#define HEXAGONPROFITRECOGNIZER_H
+
+#include "HexagonInstrInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/CodeGen/DFAPacketizer.h"
+#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+
+namespace llvm {
+
+class HexagonHazardRecognizer : public ScheduleHazardRecognizer {
+ DFAPacketizer *Resources;
+ const HexagonInstrInfo *TII;
+ unsigned PacketNum;
+ // If the packet contains a potential dot cur instruction. This is
+ // used for the scheduling priority function.
+ SUnit *UsesDotCur;
+ // The packet number when a dor cur is emitted. If its use is not generated
+ // in the same packet, then try to wait another cycle before emitting.
+ int DotCurPNum;
+ // The set of registers defined by instructions in the current packet.
+ SmallSet<unsigned, 8> RegDefs;
+
+public:
+ HexagonHazardRecognizer(const InstrItineraryData *II,
+ const HexagonInstrInfo *HII,
+ const HexagonSubtarget &ST)
+ : Resources(ST.createDFAPacketizer(II)), TII(HII), PacketNum(0),
+ UsesDotCur(nullptr), DotCurPNum(-1) { }
+
+ ~HexagonHazardRecognizer() {
+ if (Resources)
+ delete Resources;
+ }
+
+ /// This callback is invoked when a new block of instructions is about to be
+ /// scheduled. The hazard state is set to an initialized state.
+ virtual void Reset() override;
+
+ /// Return the hazard type of emitting this node. There are three
+ /// possible results. Either:
+ /// * NoHazard: it is legal to issue this instruction on this cycle.
+ /// * Hazard: issuing this instruction would stall the machine. If some
+ /// other instruction is available, issue it first.
+ virtual HazardType getHazardType(SUnit *SU, int stalls) override;
+
+ /// This callback is invoked when an instruction is emitted to be scheduled,
+ /// to advance the hazard state.
+ virtual void EmitInstruction(SUnit *) override;
+
+ /// This callback may be invoked if getHazardType returns NoHazard. If, even
+ /// though there is no hazard, it would be better to schedule another
+ /// available instruction, this callback should return true.
+ virtual bool ShouldPreferAnother(SUnit *) override;
+
+ /// This callback is invoked whenever the next top-down instruction to be
+ /// scheduled cannot issue in the current cycle, either because of latency
+ /// or resource conflicts. This should increment the internal state of the
+ /// hazard recognizer so that previously "Hazard" instructions will now not
+ /// be hazards.
+ virtual void AdvanceCycle() override;
+};
+
+} // end namespace llvm
+
+#endif // HEXAGONPROFITRECOGNIZER_H
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