[llvm] r277143 - [Hexagon] Implement DFA based hazard recognizer
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 06:59:10 PDT 2016
Author: kparzysz
Date: Fri Jul 29 08:59:09 2016
New Revision: 277143
URL: http://llvm.org/viewvc/llvm-project?rev=277143&view=rev
Log:
[Hexagon] Implement DFA based hazard recognizer
The post register allocator scheduler can generate poor schedules
because the scoreboard hazard recognizer is unable to identify
hazards for Hexagon precisely. Instead, Hexagon should use a DFA
based hazard recognizer.
Patch by Brendon Cahoon.
Modified:
llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=277143&r1=277142&r2=277143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Fri Jul 29 08:59:09 2016
@@ -32,6 +32,7 @@ add_llvm_target(HexagonCodeGen
HexagonGenMux.cpp
HexagonGenPredicate.cpp
HexagonHardwareLoops.cpp
+ HexagonHazardRecognizer.cpp
HexagonInstrInfo.cpp
HexagonISelDAGToDAG.cpp
HexagonISelLowering.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=277143&r1=277142&r2=277143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Jul 29 08:59:09 2016
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
+#include "HexagonHazardRecognizer.h"
#include "HexagonInstrInfo.h"
-#include "Hexagon.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/STLExtras.h"
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
@@ -39,8 +40,6 @@ using namespace llvm;
#include "HexagonGenInstrInfo.inc"
#include "HexagonGenDFAPacketizer.inc"
-using namespace llvm;
-
cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
"packetization boundary."));
@@ -67,6 +66,10 @@ static cl::opt<bool> EnableACCForwarding
static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
+static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
+ cl::init(true), cl::Hidden, cl::ZeroOrMore,
+ cl::desc("Use the DFA based hazard recognizer."));
+
///
/// Constants for Hexagon instructions.
///
@@ -1433,6 +1436,10 @@ unsigned HexagonInstrInfo::getInlineAsmL
ScheduleHazardRecognizer*
HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
const InstrItineraryData *II, const ScheduleDAG *DAG) const {
+ if (UseDFAHazardRec) {
+ auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
+ return new HexagonHazardRecognizer(II, this, HST);
+ }
return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
}
More information about the llvm-commits
mailing list