[PATCH] D22933: DAG: avoid truncating a sign extended operand when test equality against zero

[Weiming Zhao via llvm-commits]

weimingz marked an inline comment as done.

================
Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:961
@@ +960,3 @@
+      // avoid truncation.
+    } else if ((OpL->getOpcode() == ISD::AssertSext &&
+                isa<ConstantSDNode>(OpR) &&
----------------
t.p.northover wrote:
> I think there are a couple of issues here.
> 
> First, I think you need to check that the AssertSext is from the same type (or smaller) as the original values (like above). Otherwise there could still be unknown rubbish in between the two cut-offs.
> 
> Second, don't all of these cases apply equally to AssertZext?
AssertZExt is handled in later DAG combining because it can computes the known bits. 

================
Comment at: test/CodeGen/ARM/interrupt-attr.ll:52-54
@@ -51,1 +51,5 @@
 
+define arm_aapcscc void @irq_fn_tailcall() alignstack(8)  "interrupt"="IRQ" {
+  ; Must save all registers except banked sp and lr (we save lr anyway because
+  ; we actually need it at the end to execute the return ourselves).
+
----------------
t.p.northover wrote:
> This looks unrelated?
sorry. I added the wrong file. I suppose to add the test case for it.


Repository:
  rL LLVM

https://reviews.llvm.org/D22933