[PATCH] D22933: DAG: avoid truncating a sign extended operand when test equality against zero

[Tim Northover via llvm-commits]

t.p.northover added a subscriber: t.p.northover.

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Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:959-960
@@ -958,1 +958,4 @@
       NewRHS = OpR;
+      // If one operand is sign extension and the other is constant zero, we can
+      // avoid truncation.
+    } else if ((OpL->getOpcode() == ISD::AssertSext &&
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The comment should probably be in the block it belongs to.

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Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:961
@@ +960,3 @@
+      // avoid truncation.
+    } else if ((OpL->getOpcode() == ISD::AssertSext &&
+                isa<ConstantSDNode>(OpR) &&
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I think there are a couple of issues here.

First, I think you need to check that the AssertSext is from the same type (or smaller) as the original values (like above). Otherwise there could still be unknown rubbish in between the two cut-offs.

Second, don't all of these cases apply equally to AssertZext?

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Comment at: test/CodeGen/ARM/interrupt-attr.ll:52-54
@@ -51,1 +51,5 @@
 
+define arm_aapcscc void @irq_fn_tailcall() alignstack(8)  "interrupt"="IRQ" {
+  ; Must save all registers except banked sp and lr (we save lr anyway because
+  ; we actually need it at the end to execute the return ourselves).
+
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This looks unrelated?


Repository:
  rL LLVM

https://reviews.llvm.org/D22933