[PATCH] D22680: [mips][fastisel] Handle 0-4 arguments without SelectionDAG.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 28 08:27:16 PDT 2016
dsanders added inline comments.
================
Comment at: lib/Target/Mips/MipsFastISel.cpp:1272
@@ +1271,3 @@
+ if (CC != CallingConv::C) {
+ DEBUG(dbgs() << ".. gave up (wrong calling convention)\n");
+ return false;
----------------
sdardis wrote:
> ".. gave up (calling convention is not C)" is clearer here I think.
I unintentionally committed before fixing this so I made this change in r276984
================
Comment at: test/CodeGen/Mips/Fast-ISel/callabi.ll:186-190
@@ -185,7 +185,7 @@
; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]]
; 32R2-DAG: sw $4, 16($sp)
; 32R2-DAG: move $4, $[[T4]]
; 32R2-DAG: seb $5, $[[T1]]
; 32R2-DAG: seb $6, $[[T2]]
; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
; 32R2: seb $7, $[[T5]]
----------------
sdardis wrote:
> Stack slot has a 24 byte offset.
It was 16 when I ran 'ninja check' just before the commit so I haven't made this change.
================
Comment at: test/CodeGen/Mips/Fast-ISel/callabi.ll:221-225
@@ -220,7 +220,7 @@
; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]]
; 32R2-DAG: sw $4, 16($sp)
; 32R2-DAG: move $4, $[[T4]]
; 32R2-DAG: seh $5, $[[T1]]
; 32R2-DAG: seh $6, $[[T2]]
; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
; 32R2: seh $7, $[[T5]]
----------------
sdardis wrote:
> Stack slot has 24 byte offset here as well.
It was 16 when I ran 'ninja check' just before the commit so I haven't made this change.
https://reviews.llvm.org/D22680
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