[PATCH] D22680: [mips][fastisel] Handle 0-4 arguments without SelectionDAG.

[Simon Dardis via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LTGM though callabi.ll (functions cxcccc & cxhhhh) has some extra changes with my local copy of LLVM. It appears there's another frame object object being allocated which changes the offsets. Ok with that test fixed.


================
Comment at: lib/Target/Mips/MipsFastISel.cpp:1272
@@ +1271,3 @@
+  if (CC != CallingConv::C) {
+    DEBUG(dbgs() << ".. gave up (wrong calling convention)\n");
+    return false;
----------------
".. gave up (calling convention is not C)" is clearer here I think.

================
Comment at: test/CodeGen/Mips/Fast-ISel/callabi.ll:186-190
@@ -185,7 +185,7 @@
   ; 32R2-DAG:       seb     $[[T4:[0-9]+]], $[[T0]]
   ; 32R2-DAG:       sw      $4, 16($sp)
   ; 32R2-DAG:       move    $4, $[[T4]]
   ; 32R2-DAG:       seb     $5, $[[T1]]
   ; 32R2-DAG:       seb     $6, $[[T2]]
   ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
   ; 32R2:           seb     $7, $[[T5]]
----------------
Stack slot has a 24 byte offset.

================
Comment at: test/CodeGen/Mips/Fast-ISel/callabi.ll:221-225
@@ -220,7 +220,7 @@
   ; 32R2-DAG:       seh     $[[T4:[0-9]+]], $[[T0]]
   ; 32R2-DAG:       sw      $4, 16($sp)
   ; 32R2-DAG:       move    $4, $[[T4]]
   ; 32R2-DAG:       seh     $5, $[[T1]]
   ; 32R2-DAG:       seh     $6, $[[T2]]
   ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
   ; 32R2:           seh     $7, $[[T5]]
----------------
Stack slot has 24 byte offset here as well.


https://reviews.llvm.org/D22680