[llvm] r276266 - ExecutionDepsFix - Fix bug in clearance calculation

[Marina Yatsina via llvm-commits]

Author: myatsina
Date: Thu Jul 21 07:37:07 2016
New Revision: 276266

URL: http://llvm.org/viewvc/llvm-project?rev=276266&view=rev
Log:
ExecutionDepsFix - Fix bug in clearance calculation

The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.

Differential Revision: http://reviews.llvm.org/D22580


Modified:
    llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
    llvm/trunk/test/CodeGen/X86/break-false-dep.ll

Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=276266&r1=276265&r2=276266&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Thu Jul 21 07:37:07 2016
@@ -520,8 +520,6 @@ void ExeDepsFix::processDefs(MachineInst
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg())
       continue;
-    if (MO.isImplicit())
-      break;
     if (MO.isUse())
       continue;
     for (int rx : regIndices(MO.getReg())) {

Modified: llvm/trunk/test/CodeGen/X86/break-false-dep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-false-dep.ll?rev=276266&r1=276265&r2=276266&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/break-false-dep.ll (original)
+++ llvm/trunk/test/CodeGen/X86/break-false-dep.ll Thu Jul 21 07:37:07 2016
@@ -199,3 +199,13 @@ for.end16:
 ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
 ;AVX-NEXT: vmovsd [[XMM0]],
 }
+
+define double @inlineasmdep(i64 %arg) {
+top:
+  tail call void asm sideeffect "", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+  %tmp1 = sitofp i64 %arg to double
+  ret double %tmp1
+;AVX-LABEL:@inlineasmdep
+;AVX: vxorps  [[XMM0:%xmm[0-9]+]], [[XMM0]], [[XMM0]]
+;AVX-NEXT: vcvtsi2sdq {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
+}