[PATCH] D22347: [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Two major changes required.

a) cfc1 is already defined for microMIPS in MicroMipsInstrFPU.def and was not re-encoded for R6, so we don't need to reimplement it here.

b) We don't currently define cfc2 for microMIPS, so that instruction can be moved to MicroMipsInstrInfo.td and adjusted.

Thanks.


================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:78-81
@@ -77,2 +77,6 @@
 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
+class CFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"cfc1", 0b01000000>;
+class CFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"cfc2", 0b1100110100>;
+class CTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"ctc1", 0b01100000>;
+class CTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"ctc2", 0b1101110100>;
 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
----------------
We don't need to implement cfc for microMIPSR6 as it was not re-encoded for R6. cfc2 was also not re-encoded for R6, so it should be added to MicroMipsInstrInfo.td.  

================
Comment at: lib/Target/Mips/MipsInstrFPU.td:364-367
@@ -363,4 +363,6 @@
 /// Move Control Registers From/To CPU Registers
-def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
-def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
+def CFC1 : MMRel, StdMMR6Rel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
+           MFC1_FM<2>;
+def CTC1 : MMRel, StdMMR6Rel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
+           MFC1_FM<6>;
 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
----------------
These instructions need to be marked as ISA_MIPS32, and the StdMMR6Rel can be dropped.

================
Comment at: test/MC/Disassembler/Mips/micromips32r6/valid.txt:65-68
@@ -64,2 +64,6 @@
 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
+0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
+0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
+0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
 0x00 0x00 0xe3 0x7c # CHECK: deret
----------------
These should also be duplicated into the other micromips directories in disassembler.

================
Comment at: test/MC/Mips/micromips32r6/valid.s:50-53
@@ -49,2 +49,6 @@
   clz $sp, $gp             # CHECK: clz $sp, $gp        # encoding: [0x03,0x80,0xe8,0x50]
+  cfc1 $1, $2              # CHECK: cfc1 $1, $2         # encoding: [0x54,0x22,0x10,0x3b]
+  cfc2 $3, $4              # CHECK: cfc2 $3, $4         # encoding: [0x00,0x64,0xcd,0x3c]
+  ctc1 $5, $6              # CHECK: ctc1 $5, $6         # encoding: [0x54,0xa6,0x18,0x3b]
+  ctc2 $7, $8              # CHECK: ctc2 $7, $8         # encoding: [0x00,0xe8,0xdd,0x3c]
   div $3, $4, $5           # CHECK: div $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x18]
----------------
Likewise these tests should be duplicated into test/MC/Mips/micromips/.


https://reviews.llvm.org/D22347