[llvm] r275427 - [X86] Decode MPX BND registers.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 07:53:21 PDT 2016
Author: ab
Date: Thu Jul 14 09:53:21 2016
New Revision: 275427
URL: http://llvm.org/viewvc/llvm-project?rev=275427&view=rev
Log:
[X86] Decode MPX BND registers.
We were able to assemble, but not disassemble.
Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit
the uint8_t max. The control registers were already squarely above
it, but I don't think they ever go in .r/m, only in .reg.
I also did notice an extra REX.W in our encoding, but I think that's
fine.
Modified:
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
llvm/trunk/test/MC/X86/mpx-encodings.s
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=275427&r1=275426&r2=275427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Thu Jul 14 09:53:21 2016
@@ -1450,10 +1450,10 @@ static int readModRM(struct InternalInst
}
#define GENERIC_FIXUP_FUNC(name, base, prefix) \
- static uint8_t name(struct InternalInstruction *insn, \
- OperandType type, \
- uint8_t index, \
- uint8_t *valid) { \
+ static uint16_t name(struct InternalInstruction *insn, \
+ OperandType type, \
+ uint8_t index, \
+ uint8_t *valid) { \
*valid = 1; \
switch (type) { \
default: \
@@ -1503,6 +1503,10 @@ static int readModRM(struct InternalInst
return prefix##_DR0 + index; \
case TYPE_CONTROLREG: \
return prefix##_CR0 + index; \
+ case TYPE_BNDR: \
+ if (index > 3) \
+ *valid = 0; \
+ return prefix##_BND0 + index; \
} \
}
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h?rev=275427&r1=275426&r2=275427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h Thu Jul 14 09:53:21 2016
@@ -369,6 +369,12 @@ namespace X86Disassembler {
ENTRY(CR14) \
ENTRY(CR15)
+#define REGS_BOUND \
+ ENTRY(BND0) \
+ ENTRY(BND1) \
+ ENTRY(BND2) \
+ ENTRY(BND3)
+
#define ALL_EA_BASES \
EA_BASES_16BIT \
EA_BASES_32BIT \
@@ -391,6 +397,7 @@ namespace X86Disassembler {
REGS_SEGMENT \
REGS_DEBUG \
REGS_CONTROL \
+ REGS_BOUND \
ENTRY(RIP)
/// \brief All possible values of the base field for effective-address
Modified: llvm/trunk/test/MC/X86/mpx-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/mpx-encodings.s?rev=275427&r1=275426&r2=275427&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/mpx-encodings.s (original)
+++ llvm/trunk/test/MC/X86/mpx-encodings.s Thu Jul 14 09:53:21 2016
@@ -1,38 +1,41 @@
-// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64-- -mattr=+mpx --show-encoding %s |\
+// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple x86_64-- -mattr=+mpx -filetype=obj %s |\
+// RUN: llvm-objdump -d - -mattr=+mpx | FileCheck %s
// CHECK: bndmk (%rax), %bnd0
-// CHECK: encoding: [0xf3,0x48,0x0f,0x1b,0x00]
+// ENCODING: encoding: [0xf3,0x48,0x0f,0x1b,0x00]
bndmk (%rax), %bnd0
// CHECK: bndmk 1024(%rax), %bnd1
-// CHECK: encoding: [0xf3,0x48,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
+// ENCODING: encoding: [0xf3,0x48,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndmk 1024(%rax), %bnd1
// CHECK: bndmov %bnd2, %bnd1
-// CHECK: encoding: [0x66,0x0f,0x1b,0xd1]
+// ENCODING: encoding: [0x66,0x0f,0x1b,0xd1]
bndmov %bnd2, %bnd1
// CHECK: bndmov %bnd1, 1024(%r9)
-// CHECK: encoding: [0x66,0x49,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
+// ENCODING: encoding: [0x66,0x49,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
bndmov %bnd1, 1024(%r9)
// CHECK: bndstx %bnd1, 1024(%rax)
-// CHECK: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
+// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndstx %bnd1, 1024(%rax)
// CHECK: bndldx 1024(%r8), %bnd1
-// CHECK: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
+// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
bndldx 1024(%r8), %bnd1
// CHECK: bndcl 121(%r10), %bnd1
-// CHECK: encoding: [0xf3,0x49,0x0f,0x1a,0x4a,0x79]
+// ENCODING: encoding: [0xf3,0x49,0x0f,0x1a,0x4a,0x79]
bndcl 121(%r10), %bnd1
// CHECK: bndcn 121(%rcx), %bnd3
-// CHECK: encoding: [0xf2,0x48,0x0f,0x1b,0x59,0x79]
+// ENCODING: encoding: [0xf2,0x48,0x0f,0x1b,0x59,0x79]
bndcn 121(%rcx), %bnd3
// CHECK: bndcu %rdx, %bnd3
-// CHECK: encoding: [0xf2,0x48,0x0f,0x1a,0xda]
+// ENCODING: encoding: [0xf2,0x48,0x0f,0x1a,0xda]
bndcu %rdx, %bnd3
-
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