[llvm] r275252 - AMDGPU: WQM cleanups
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 12 22:55:16 PDT 2016
Author: arsenm
Date: Wed Jul 13 00:55:15 2016
New Revision: 275252
URL: http://llvm.org/viewvc/llvm-project?rev=275252&view=rev
Log:
AMDGPU: WQM cleanups
- Add new TTI instruction checks
- Don't use const for blocks that are mutated.
- Checking isBranch and isTerminator should be redundant
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=275252&r1=275251&r2=275252&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Wed Jul 13 00:55:15 2016
@@ -350,6 +350,14 @@ public:
return get(Opcode).TSFlags & SIInstrFlags::DPP;
}
+ static bool isScalarUnit(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
+ }
+
+ static bool usesVM_CNT(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
+ }
+
bool isVGPRCopy(const MachineInstr &MI) const {
assert(MI.isCopy());
unsigned Dest = MI.getOperand(0).getReg();
Modified: llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp?rev=275252&r1=275251&r2=275252&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp Wed Jul 13 00:55:15 2016
@@ -53,13 +53,10 @@
#include "AMDGPUSubtarget.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
-#include "llvm/CodeGen/MachineDominanceFrontier.h"
-#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/IR/Constants.h"
using namespace llvm;
@@ -84,12 +81,12 @@ struct BlockInfo {
};
struct WorkItem {
- const MachineBasicBlock *MBB = nullptr;
- const MachineInstr *MI = nullptr;
+ MachineBasicBlock *MBB = nullptr;
+ MachineInstr *MI = nullptr;
WorkItem() {}
- WorkItem(const MachineBasicBlock *MBB) : MBB(MBB) {}
- WorkItem(const MachineInstr *MI) : MI(MI) {}
+ WorkItem(MachineBasicBlock *MBB) : MBB(MBB) {}
+ WorkItem(MachineInstr *MI) : MI(MI) {}
};
class SIWholeQuadMode : public MachineFunctionPass {
@@ -99,13 +96,13 @@ private:
MachineRegisterInfo *MRI;
DenseMap<const MachineInstr *, InstrInfo> Instructions;
- DenseMap<const MachineBasicBlock *, BlockInfo> Blocks;
+ DenseMap<MachineBasicBlock *, BlockInfo> Blocks;
SmallVector<const MachineInstr *, 2> ExecExports;
SmallVector<MachineInstr *, 1> LiveMaskQueries;
- char scanInstructions(MachineFunction &MF, std::vector<WorkItem>& Worklist);
- void propagateInstruction(const MachineInstr &MI, std::vector<WorkItem>& Worklist);
- void propagateBlock(const MachineBasicBlock &MBB, std::vector<WorkItem>& Worklist);
+ char scanInstructions(MachineFunction &MF, std::vector<WorkItem> &Worklist);
+ void propagateInstruction(MachineInstr &MI, std::vector<WorkItem> &Worklist);
+ void propagateBlock(MachineBasicBlock &MBB, std::vector<WorkItem> &Worklist);
char analyzeFunction(MachineFunction &MF);
void toExact(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
@@ -138,10 +135,8 @@ public:
char SIWholeQuadMode::ID = 0;
-INITIALIZE_PASS_BEGIN(SIWholeQuadMode, DEBUG_TYPE,
- "SI Whole Quad Mode", false, false)
-INITIALIZE_PASS_END(SIWholeQuadMode, DEBUG_TYPE,
- "SI Whole Quad Mode", false, false)
+INITIALIZE_PASS(SIWholeQuadMode, DEBUG_TYPE,
+ "SI Whole Quad Mode", false, false)
char &llvm::SIWholeQuadModeID = SIWholeQuadMode::ID;
@@ -166,8 +161,7 @@ char SIWholeQuadMode::scanInstructions(M
if (TII->isWQM(Opcode) || TII->isDS(Opcode)) {
Flags = StateWQM;
- } else if (TII->get(Opcode).mayStore() &&
- (MI.getDesc().TSFlags & SIInstrFlags::VM_CNT)) {
+ } else if (MI.mayStore() && TII->usesVM_CNT(MI)) {
Flags = StateExact;
} else {
// Handle export instructions with the exec mask valid flag set
@@ -214,16 +208,15 @@ char SIWholeQuadMode::scanInstructions(M
return GlobalFlags;
}
-void SIWholeQuadMode::propagateInstruction(const MachineInstr &MI,
+void SIWholeQuadMode::propagateInstruction(MachineInstr &MI,
std::vector<WorkItem>& Worklist) {
- const MachineBasicBlock &MBB = *MI.getParent();
+ MachineBasicBlock *MBB = MI.getParent();
InstrInfo II = Instructions[&MI]; // take a copy to prevent dangling references
- BlockInfo &BI = Blocks[&MBB];
+ BlockInfo &BI = Blocks[MBB];
// Control flow-type instructions that are followed by WQM computations
// must themselves be in WQM.
- if ((II.OutNeeds & StateWQM) && !(II.Needs & StateWQM) &&
- (MI.isBranch() || MI.isTerminator())) {
+ if ((II.OutNeeds & StateWQM) && !(II.Needs & StateWQM) && MI.isTerminator()) {
Instructions[&MI].Needs = StateWQM;
II.Needs = StateWQM;
}
@@ -232,11 +225,11 @@ void SIWholeQuadMode::propagateInstructi
BI.Needs |= II.Needs;
if ((BI.InNeeds | II.Needs) != BI.InNeeds) {
BI.InNeeds |= II.Needs;
- Worklist.push_back(&MBB);
+ Worklist.push_back(MBB);
}
// Propagate backwards within block
- if (const MachineInstr *PrevMI = MI.getPrevNode()) {
+ if (MachineInstr *PrevMI = MI.getPrevNode()) {
char InNeeds = II.Needs | II.OutNeeds;
if (!PrevMI->isPHI()) {
InstrInfo &PrevII = Instructions[PrevMI];
@@ -267,9 +260,8 @@ void SIWholeQuadMode::propagateInstructi
if (!TargetRegisterInfo::isVirtualRegister(Use.getReg()))
continue;
- for (const MachineOperand &Def : MRI->def_operands(Use.getReg())) {
- const MachineInstr *DefMI = Def.getParent();
- InstrInfo &DefII = Instructions[DefMI];
+ for (MachineInstr &DefMI : MRI->def_instructions(Use.getReg())) {
+ InstrInfo &DefII = Instructions[&DefMI];
// Obviously skip if DefMI is already flagged as NeedWQM.
//
@@ -281,18 +273,18 @@ void SIWholeQuadMode::propagateInstructi
continue;
DefII.Needs = StateWQM;
- Worklist.push_back(DefMI);
+ Worklist.push_back(&DefMI);
}
}
}
-void SIWholeQuadMode::propagateBlock(const MachineBasicBlock &MBB,
+void SIWholeQuadMode::propagateBlock(MachineBasicBlock &MBB,
std::vector<WorkItem>& Worklist) {
- BlockInfo BI = Blocks[&MBB]; // take a copy to prevent dangling references
+ BlockInfo BI = Blocks[&MBB]; // Make a copy to prevent dangling references.
// Propagate through instructions
if (!MBB.empty()) {
- const MachineInstr *LastMI = &*MBB.rbegin();
+ MachineInstr *LastMI = &*MBB.rbegin();
InstrInfo &LastII = Instructions[LastMI];
if ((LastII.OutNeeds | BI.OutNeeds) != LastII.OutNeeds) {
LastII.OutNeeds |= BI.OutNeeds;
@@ -301,7 +293,7 @@ void SIWholeQuadMode::propagateBlock(con
}
// Predecessor blocks must provide for our WQM/Exact needs.
- for (const MachineBasicBlock *Pred : MBB.predecessors()) {
+ for (MachineBasicBlock *Pred : MBB.predecessors()) {
BlockInfo &PredBI = Blocks[Pred];
if ((PredBI.OutNeeds | BI.InNeeds) == PredBI.OutNeeds)
continue;
@@ -311,9 +303,8 @@ void SIWholeQuadMode::propagateBlock(con
Worklist.push_back(Pred);
}
- // All successors must be prepared to accept the same set of WQM/Exact
- // data.
- for (const MachineBasicBlock *Succ : MBB.successors()) {
+ // All successors must be prepared to accept the same set of WQM/Exact data.
+ for (MachineBasicBlock *Succ : MBB.successors()) {
BlockInfo &SuccBI = Blocks[Succ];
if ((SuccBI.InNeeds | BI.OutNeeds) == SuccBI.InNeeds)
continue;
@@ -394,8 +385,7 @@ void SIWholeQuadMode::processBlock(Machi
++II;
// Skip instructions that are not affected by EXEC
- if (MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD) &&
- !MI.isBranch() && !MI.isTerminator())
+ if (TII->isScalarUnit(MI) && !MI.isTerminator())
continue;
// Generic instructions such as COPY will either disappear by register
@@ -421,7 +411,7 @@ void SIWholeQuadMode::processBlock(Machi
// Make sure to switch to Exact mode before the end of the block when
// Exact and only Exact is needed further downstream.
- if (OutNeeds == StateExact && (MI.isBranch() || MI.isTerminator())) {
+ if (OutNeeds == StateExact && MI.isTerminator()) {
assert(Needs == 0);
Needs = StateExact;
}
@@ -456,7 +446,7 @@ void SIWholeQuadMode::processBlock(Machi
void SIWholeQuadMode::lowerLiveMaskQueries(unsigned LiveMaskReg) {
for (MachineInstr *MI : LiveMaskQueries) {
- DebugLoc DL = MI->getDebugLoc();
+ const DebugLoc &DL = MI->getDebugLoc();
unsigned Dest = MI->getOperand(0).getReg();
BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
.addReg(LiveMaskReg);
@@ -512,9 +502,8 @@ bool SIWholeQuadMode::runOnMachineFuncti
lowerLiveMaskQueries(LiveMaskReg);
// Handle the general case
- for (const auto &BII : Blocks)
- processBlock(const_cast<MachineBasicBlock &>(*BII.first), LiveMaskReg,
- BII.first == &*MF.begin());
+ for (auto BII : Blocks)
+ processBlock(*BII.first, LiveMaskReg, BII.first == &*MF.begin());
return true;
}
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