[llvm] r275143 - [Kryo] Enable ZCZeroing feature
Haicheng Wu via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 11 19:04:01 PDT 2016
Author: haicheng
Date: Mon Jul 11 21:04:01 2016
New Revision: 275143
URL: http://llvm.org/viewvc/llvm-project?rev=275143&view=rev
Log:
[Kryo] Enable ZCZeroing feature
This feature uses immediate #0 to zero a register.
Differential Revision: http://reviews.llvm.org/D19985
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=275143&r1=275142&r2=275143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Mon Jul 11 21:04:01 2016
@@ -237,7 +237,8 @@ def ProcKryo : SubtargetFeature<"kryo
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler,
- FeaturePredictableSelectIsExpensive
+ FeaturePredictableSelectIsExpensive,
+ FeatureZCZeroing
]>;
def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll?rev=275143&r1=275142&r2=275143&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll Mon Jul 11 21:04:01 2016
@@ -1,44 +1,52 @@
-; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefix=CYCLONE --check-prefix=ALL
+; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefix=KRYO --check-prefix=ALL
+
; rdar://11481771
; rdar://13713797
define void @t1() nounwind ssp {
entry:
-; CHECK-LABEL: t1:
-; CHECK-NOT: fmov
-; CHECK: movi.2d v0, #0000000000000000
-; CHECK: movi.2d v1, #0000000000000000
-; CHECK: movi.2d v2, #0000000000000000
-; CHECK: movi.2d v3, #0000000000000000
+; ALL-LABEL: t1:
+; ALL-NOT: fmov
+; CYCLONE: movi.2d v0, #0000000000000000
+; CYCLONE: movi.2d v1, #0000000000000000
+; CYCLONE: movi.2d v2, #0000000000000000
+; CYCLONE: movi.2d v3, #0000000000000000
+; KRYO: movi v0.2d, #0000000000000000
+; KRYO: mov v1.16b, v0.16b
+; KRYO: mov v2.16b, v0.16b
+; KRYO: mov v3.16b, v0.16b
tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind
ret void
}
define void @t2() nounwind ssp {
entry:
-; CHECK-LABEL: t2:
-; CHECK-NOT: mov w0, wzr
-; CHECK: mov w0, #0
-; CHECK: mov w1, #0
+; ALL-LABEL: t2:
+; ALL-NOT: mov w0, wzr
+; ALL: mov w0, #0
+; ALL: mov w1, #0
tail call void @bari(i32 0, i32 0) nounwind
ret void
}
define void @t3() nounwind ssp {
entry:
-; CHECK-LABEL: t3:
-; CHECK-NOT: mov x0, xzr
-; CHECK: mov x0, #0
-; CHECK: mov x1, #0
+; ALL-LABEL: t3:
+; ALL-NOT: mov x0, xzr
+; ALL: mov x0, #0
+; ALL: mov x1, #0
tail call void @barl(i64 0, i64 0) nounwind
ret void
}
define void @t4() nounwind ssp {
-; CHECK-LABEL: t4:
-; CHECK-NOT: fmov
-; CHECK: movi.2d v0, #0000000000000000
-; CHECK: movi.2d v1, #0000000000000000
+; ALL-LABEL: t4:
+; ALL-NOT: fmov
+; CYCLONE: movi.2d v0, #0000000000000000
+; CYCLONE: movi.2d v1, #0000000000000000
+; KRYO: movi v0.2d, #0000000000000000
+; KRYO: mov v1.16b, v0.16b
tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
ret void
}
@@ -50,9 +58,9 @@ declare void @barf(float, float)
; We used to produce spills+reloads for a Q register with zero cycle zeroing
; enabled.
-; CHECK-LABEL: foo:
-; CHECK-NOT: str {{q[0-9]+}}
-; CHECK-NOT: ldr {{q[0-9]+}}
+; ALL-LABEL: foo:
+; ALL-NOT: str {{q[0-9]+}}
+; ALL-NOT: ldr {{q[0-9]+}}
define double @foo(i32 %n) {
entry:
br label %for.body
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