[PATCH] D21826: AArch64: Change modeling of zero cycle zeroing.

[Chad Rosier via llvm-commits]

mcrosier added a comment.

This looks reasonable to me..

I've asked @haicheng to review/investigate as well to make sure he's no longer seeing the spill code.


================
Comment at: lib/Target/AArch64/AArch64AsmPrinter.cpp:432
@@ +431,3 @@
+      assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
+      DestReg = AArch64::Q0 + (DestReg - AArch64::Q0);
+    }
----------------
rovka wrote:
> Shouldn't this be -AArch64::D0?
Yes, I believe @rovka is correct.


Repository:
  rL LLVM

http://reviews.llvm.org/D21826