[llvm] r273544 - [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCI
Mike Aizatsky via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 24 11:51:25 PDT 2016
Diana,
I'm not completely sure, but it looks like this change breaks thumbv7 bot.
Could you take a look?
First failure:
http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/3667
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#141 _ZNK4llvm6SDNode12getValueTypeEj.exit1085 (0xae98f04)
- instruction: %R0<def> = t2ADDri
- operand 6: %R0<imp-use>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: BUNDLE
- operand 145: %Q10_Q11_Q12_Q13<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: BUNDLE
- operand 160: %Q9_Q10_Q11_Q12<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: BUNDLE
- operand 169: %Q8_Q9_Q10_Q11<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: BUNDLE
- operand 178: %Q0_Q1_Q2_Q3<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: tBL
- operand 31: %Q10_Q11_Q12_Q13<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: tBL
- operand 59: %Q9_Q10_Q11_Q12<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: tBL
- operand 74: %Q8_Q9_Q10_Q11<imp-use,kill>
*** Bad machine code: Using an undefined physical register ***
- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE
- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)
- instruction: tBL
- operand 86: %Q0_Q1_Q2_Q3<imp-use,kill>
fatal error: error in backend: Found 9 machine code errors.
clang-3.9: error: clang frontend command failed with exit code 70 (use -v
to see invocation)
clang version 3.9.0 (trunk 273559)
Target: armv7l-unknown-linux-gnueabihf
Thread model: posix
InstalledDir:
/home/linaro/devel/buildbot/clang-cmake-thumbv7-a15-full-sh/stage1.install/bin
clang-3.9: note: diagnostic msg: PLEASE submit a bug report to
http://llvm.org/bugs/ and include the crash backtrace, preprocessed source,
and associated run script.
clang-3.9: note: diagnostic msg:
********************
PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang-3.9: note: diagnostic msg: /tmp/DAGCombiner-5075b2.cpp
clang-3.9: note: diagnostic msg: /tmp/DAGCombiner-5075b2.sh
clang-3.9: note: diagnostic msg:
********************
ninja: build stopped: subcommand failed.
program finished with exit code 1
elapsedTime=1657.193716
On Thu, Jun 23, 2016 at 12:54 AM Diana Picus via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: rovka
> Date: Thu Jun 23 02:47:35 2016
> New Revision: 273544
>
> URL: http://llvm.org/viewvc/llvm-project?rev=273544&view=rev
> Log:
> [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCI
>
> This is a cleanup commit similar to r271555, but for ARM.
>
> The end goal is to get rid of the isSwift / isCortexXY / isWhatever
> methods.
>
> Since the ARM backend seems to have quite a lot of calls to these methods,
> I
> intend to submit 5-6 subtarget features at a time, instead of one big lump.
>
> Differential Revision: http://reviews.llvm.org/D21432
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARM.td
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> llvm/trunk/lib/Target/ARM/ARMSubtarget.h
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=273544&r1=273543&r2=273544&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jun 23 02:47:35 2016
> @@ -106,6 +106,44 @@ def FeatureRAS : SubtargetFeature<"ras",
> def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing",
> "true",
> "Has zero-cycle zeroing
> instructions">;
>
> +// Whether or not it may be profitable to unpredicate certain instructions
> +// during if conversion.
> +def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
> + "IsProfitableToUnpredicate",
> + "true",
> + "Is profitable to
> unpredicate">;
> +
> +// Some targets (e.g. Swift) have microcoded VGETLNi32.
> +def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
> + "HasSlowVGETLNi32", "true",
> + "Has slow VGETLNi32 - prefer
> VMOV">;
> +
> +// Some targets (e.g. Swift) have microcoded VDUP32.
> +def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
> "true",
> + "Has slow VDUP32 - prefer VMOV">;
> +
> +// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using
> NEON
> +// for scalar FP, as this allows more effective execution domain
> optimization.
> +def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr",
> "PreferVMOVSR",
> + "true", "Prefer VMOVSR">;
> +
> +// Swift has ISHST barriers compatible with Atomic Release semantics but
> weaker
> +// than ISH
> +def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst",
> "PreferISHST",
> + "true", "Prefer ISHST
> barriers">;
> +
> +// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS
> from
> +// VFP to NEON, as an execution domain optimization.
> +def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs",
> "UseNEONForFPMovs",
> + "true", "Convert VMOVSR, VMOVRS, VMOVS to
> NEON">;
> +
> +// Some processors benefit from using NEON instructions for scalar
> +// single-precision FP operations. This affects instruction selection and
> should
> +// only be enabled if the handling of denormals is not important.
> +def FeatureNEONForFP : SubtargetFeature<"neonfp",
> "UseNEONForSinglePrecisionFP",
> + "true",
> + "Use NEON for single precision
> FP">;
> +
> // Some processors have FP multiply-accumulate instructions that don't
> // play nicely with other VFP / NEON instructions, and it's generally
> better
> // to just not use them.
> @@ -117,12 +155,6 @@ def FeatureVMLxForwarding : SubtargetFea
> "HasVMLxForwarding", "true",
> "Has multiplier accumulator
> forwarding">;
>
> -// Some processors benefit from using NEON instructions for scalar
> -// single-precision FP operations.
> -def FeatureNEONForFP : SubtargetFeature<"neonfp",
> "UseNEONForSinglePrecisionFP",
> - "true",
> - "Use NEON for single precision
> FP">;
> -
> // Disable 32-bit to 16-bit narrowing for experimentation.
> def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb",
> "true",
> "Prefer 32-bit Thumb
> instrs">;
> @@ -533,6 +565,8 @@ def : ProcessorModel<"cortex-a9", Cort
> FeatureT2XtPk,
> FeatureFP16,
>
> FeatureAvoidPartialCPSR,
> +
> FeaturePreferVMOVSR,
> +
> FeatureNEONForFPMovs,
> FeatureMP]>;
>
> // FIXME: A12 has currently the same Schedule model as A9
> @@ -596,7 +630,11 @@ def : ProcessorModel<"swift", Swif
> FeatureHWDivARM,
>
> FeatureAvoidPartialCPSR,
>
> FeatureAvoidMOVsShOp,
> -
> FeatureHasSlowFPVMLx]>;
> +
> FeatureHasSlowFPVMLx,
> +
> FeatureProfUnpredicate,
> +
> FeaturePrefISHSTBarrier,
> +
> FeatureSlowVGETLNi32,
> +
> FeatureSlowVDUP32]>;
>
> // FIXME: R4 has currently the same ProcessorModel as A8.
> def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=273544&r1=273543&r2=273544&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jun 23 02:47:35 2016
> @@ -1766,9 +1766,9 @@ isProfitableToIfCvt(MachineBasicBlock &T
> bool
> ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
> MachineBasicBlock &FMBB)
> const {
> - // Reduce false anti-dependencies to let Swift's out-of-order execution
> + // Reduce false anti-dependencies to let the target's out-of-order
> execution
> // engine do its thing.
> - return Subtarget.isSwift();
> + return Subtarget.isProfitableToUnpredicate();
> }
>
> /// getInstrPredicate - If instruction is predicated, returns its
> predicate
> @@ -4178,7 +4178,7 @@ ARMBaseInstrInfo::getExecutionDomain(con
>
> // CortexA9 is particularly picky about mixing the two and wants these
> // converted.
> - if (Subtarget.isCortexA9() && !isPredicated(*MI) &&
> + if (Subtarget.useNEONForFPMovs() && !isPredicated(*MI) &&
> (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR
> ||
> MI->getOpcode() == ARM::VMOVS))
> return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=273544&r1=273543&r2=273544&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 23 02:47:35 2016
> @@ -3024,7 +3024,8 @@ static SDValue LowerATOMIC_FENCE(SDValue
> if (Subtarget->isMClass()) {
> // Only a full system barrier exists in the M-class architectures.
> Domain = ARM_MB::SY;
> - } else if (Subtarget->isSwift() && Ord == AtomicOrdering::Release) {
> + } else if (Subtarget->preferISHSTBarriers() &&
> + Ord == AtomicOrdering::Release) {
> // Swift happens to implement ISHST barriers in a way that's
> compatible with
> // Release semantics but weaker than ISH so we'd be fools not to use
> // it. Beware: other processors probably don't!
> @@ -12236,7 +12237,7 @@ Instruction* ARMTargetLowering::emitLead
> /*FALLTHROUGH*/
> case AtomicOrdering::Release:
> case AtomicOrdering::AcquireRelease:
> - if (Subtarget->isSwift())
> + if (Subtarget->preferISHSTBarriers())
> return makeDMB(Builder, ARM_MB::ISHST);
> // FIXME: add a comment with a link to documentation justifying this.
> else
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=273544&r1=273543&r2=273544&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jun 23 02:47:35 2016
> @@ -321,19 +321,16 @@ def DontUseFusedMAC : Predicate<"!(TM.O
> " Subtarget->hasVFP4()) || "
> "Subtarget->isTargetDarwin()">;
>
> -// VGETLNi32 is microcoded on Swift - prefer VMOV.
> -def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
> -def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
> +def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">;
> +def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">;
>
> -// VDUP.32 is microcoded on Swift - prefer VMOV.
> -def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
> -def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
> +def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">;
> +def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">;
>
> -// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar
> FP, as
> -// this allows more effective execution domain optimization. See
> -// setExecutionDomain().
> -def UseVMOVSR : Predicate<"Subtarget->isCortexA9() ||
> !Subtarget->useNEONForSinglePrecisionFP()">;
> -def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() &&
> Subtarget->useNEONForSinglePrecisionFP()">;
> +def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"
> + "!Subtarget->useNEONForSinglePrecisionFP()">;
> +def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
> + "Subtarget->useNEONForSinglePrecisionFP()">;
>
> def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
> def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=273544&r1=273543&r2=273544&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jun 23 02:47:35 2016
> @@ -154,6 +154,12 @@ void ARMSubtarget::initializeEnvironment
> HasCRC = false;
> HasRAS = false;
> HasZeroCycleZeroing = false;
> + IsProfitableToUnpredicate = false;
> + HasSlowVGETLNi32 = false;
> + HasSlowVDUP32 = false;
> + PreferVMOVSR = false;
> + PreferISHST = false;
> + UseNEONForFPMovs = false;
> StrictAlign = false;
> HasDSP = false;
> UseNaClTrap = false;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=273544&r1=273543&r2=273544&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 23 02:47:35 2016
> @@ -218,6 +218,24 @@ protected:
> /// particularly effective at zeroing a VFP register.
> bool HasZeroCycleZeroing;
>
> + /// If true, if conversion may decide to leave some instructions
> unpredicated.
> + bool IsProfitableToUnpredicate;
> +
> + /// If true, VMOV will be favored over VGETLNi32.
> + bool HasSlowVGETLNi32;
> +
> + /// If true, VMOV will be favored over VDUP.
> + bool HasSlowVDUP32;
> +
> + /// If true, VMOVSR will be favored over VMOVDRR.
> + bool PreferVMOVSR;
> +
> + /// If true, ISHST barriers will be used for Release semantics.
> + bool PreferISHST;
> +
> + /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to
> NEON.
> + bool UseNEONForFPMovs;
> +
> /// StrictAlign - If true, the subtarget disallows unaligned memory
> /// accesses for some types. For details, see
> /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
> @@ -376,6 +394,12 @@ public:
> bool hasTrustZone() const { return HasTrustZone; }
> bool has8MSecExt() const { return Has8MSecExt; }
> bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
> + bool isProfitableToUnpredicate() const { return
> IsProfitableToUnpredicate; }
> + bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
> + bool hasSlowVDUP32() const { return HasSlowVDUP32; }
> + bool preferVMOVSR() const { return PreferVMOVSR; }
> + bool preferISHSTBarriers() const { return PreferISHST; }
> + bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
> bool prefers32BitThumb() const { return Pref32BitThumb; }
> bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
> bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
--
Mike
Sent from phone
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