<div dir="ltr">Diana,<div><br></div><div>I'm not completely sure, but it looks like this change breaks thumbv7 bot. Could you take a look?</div><div><br></div><div>First failure:</div><div><a href="http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/3667">http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/3667</a><br></div><div><br></div><div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#141 _ZNK4llvm6SDNode12getValueTypeEj.exit1085 (0xae98f04)</div><div>- instruction: %R0<def> = t2ADDri</div><div>- operand 6: %R0<imp-use></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: BUNDLE</div><div>- operand 145: %Q10_Q11_Q12_Q13<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: BUNDLE</div><div>- operand 160: %Q9_Q10_Q11_Q12<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: BUNDLE</div><div>- operand 169: %Q8_Q9_Q10_Q11<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: BUNDLE</div><div>- operand 178: %Q0_Q1_Q2_Q3<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: tBL</div><div>- operand 31: %Q10_Q11_Q12_Q13<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: tBL</div><div>- operand 59: %Q9_Q10_Q11_Q12<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: tBL</div><div>- operand 74: %Q8_Q9_Q10_Q11<imp-use,kill></div><div><br></div><div>*** Bad machine code: Using an undefined physical register ***</div><div>- function: _ZN12_GLOBAL__N_111DAGCombiner9visitLOADEPN4llvm6SDNodeE</div><div>- basic block: BB#498 _ZN4llvm7SDValueC2EPNS_6SDNodeEj.exit.i (0xaf583f4)</div><div>- instruction: tBL</div><div>- operand 86: %Q0_Q1_Q2_Q3<imp-use,kill></div><div>fatal error: error in backend: Found 9 machine code errors.</div><div>clang-3.9: error: clang frontend command failed with exit code 70 (use -v to see invocation)</div><div>clang version 3.9.0 (trunk 273559)</div><div>Target: armv7l-unknown-linux-gnueabihf</div><div>Thread model: posix</div><div>InstalledDir: /home/linaro/devel/buildbot/clang-cmake-thumbv7-a15-full-sh/stage1.install/bin</div><div>clang-3.9: note: diagnostic msg: PLEASE submit a bug report to <a href="http://llvm.org/bugs/">http://llvm.org/bugs/</a> and include the crash backtrace, preprocessed source, and associated run script.</div><div>clang-3.9: note: diagnostic msg: </div><div>********************</div><div><br></div><div>PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:</div><div>Preprocessed source(s) and associated run script(s) are located at:</div><div>clang-3.9: note: diagnostic msg: /tmp/DAGCombiner-5075b2.cpp</div><div>clang-3.9: note: diagnostic msg: /tmp/DAGCombiner-5075b2.sh</div><div>clang-3.9: note: diagnostic msg: </div><div><br></div><div>********************</div><div>ninja: build stopped: subcommand failed.</div><div>program finished with exit code 1</div><div>elapsedTime=1657.193716</div></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Jun 23, 2016 at 12:54 AM Diana Picus via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rovka<br>
Date: Thu Jun 23 02:47:35 2016<br>
New Revision: 273544<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=273544&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=273544&view=rev</a><br>
Log:<br>
[ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCI<br>
<br>
This is a cleanup commit similar to r271555, but for ARM.<br>
<br>
The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.<br>
<br>
Since the ARM backend seems to have quite a lot of calls to these methods, I<br>
intend to submit 5-6 subtarget features at a time, instead of one big lump.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D21432" rel="noreferrer" target="_blank">http://reviews.llvm.org/D21432</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARM.td<br>
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.h<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARM.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=273544&r1=273543&r2=273544&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=273544&r1=273543&r2=273544&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARM.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jun 23 02:47:35 2016<br>
@@ -106,6 +106,44 @@ def FeatureRAS : SubtargetFeature<"ras",<br>
def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",<br>
"Has zero-cycle zeroing instructions">;<br>
<br>
+// Whether or not it may be profitable to unpredicate certain instructions<br>
+// during if conversion.<br>
+def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",<br>
+ "IsProfitableToUnpredicate",<br>
+ "true",<br>
+ "Is profitable to unpredicate">;<br>
+<br>
+// Some targets (e.g. Swift) have microcoded VGETLNi32.<br>
+def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",<br>
+ "HasSlowVGETLNi32", "true",<br>
+ "Has slow VGETLNi32 - prefer VMOV">;<br>
+<br>
+// Some targets (e.g. Swift) have microcoded VDUP32.<br>
+def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",<br>
+ "Has slow VDUP32 - prefer VMOV">;<br>
+<br>
+// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON<br>
+// for scalar FP, as this allows more effective execution domain optimization.<br>
+def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",<br>
+ "true", "Prefer VMOVSR">;<br>
+<br>
+// Swift has ISHST barriers compatible with Atomic Release semantics but weaker<br>
+// than ISH<br>
+def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",<br>
+ "true", "Prefer ISHST barriers">;<br>
+<br>
+// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from<br>
+// VFP to NEON, as an execution domain optimization.<br>
+def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",<br>
+ "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;<br>
+<br>
+// Some processors benefit from using NEON instructions for scalar<br>
+// single-precision FP operations. This affects instruction selection and should<br>
+// only be enabled if the handling of denormals is not important.<br>
+def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",<br>
+ "true",<br>
+ "Use NEON for single precision FP">;<br>
+<br>
// Some processors have FP multiply-accumulate instructions that don't<br>
// play nicely with other VFP / NEON instructions, and it's generally better<br>
// to just not use them.<br>
@@ -117,12 +155,6 @@ def FeatureVMLxForwarding : SubtargetFea<br>
"HasVMLxForwarding", "true",<br>
"Has multiplier accumulator forwarding">;<br>
<br>
-// Some processors benefit from using NEON instructions for scalar<br>
-// single-precision FP operations.<br>
-def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",<br>
- "true",<br>
- "Use NEON for single precision FP">;<br>
-<br>
// Disable 32-bit to 16-bit narrowing for experimentation.<br>
def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",<br>
"Prefer 32-bit Thumb instrs">;<br>
@@ -533,6 +565,8 @@ def : ProcessorModel<"cortex-a9", Cort<br>
FeatureT2XtPk,<br>
FeatureFP16,<br>
FeatureAvoidPartialCPSR,<br>
+ FeaturePreferVMOVSR,<br>
+ FeatureNEONForFPMovs,<br>
FeatureMP]>;<br>
<br>
// FIXME: A12 has currently the same Schedule model as A9<br>
@@ -596,7 +630,11 @@ def : ProcessorModel<"swift", Swif<br>
FeatureHWDivARM,<br>
FeatureAvoidPartialCPSR,<br>
FeatureAvoidMOVsShOp,<br>
- FeatureHasSlowFPVMLx]>;<br>
+ FeatureHasSlowFPVMLx,<br>
+ FeatureProfUnpredicate,<br>
+ FeaturePrefISHSTBarrier,<br>
+ FeatureSlowVGETLNi32,<br>
+ FeatureSlowVDUP32]>;<br>
<br>
// FIXME: R4 has currently the same ProcessorModel as A8.<br>
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=273544&r1=273543&r2=273544&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=273544&r1=273543&r2=273544&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jun 23 02:47:35 2016<br>
@@ -1766,9 +1766,9 @@ isProfitableToIfCvt(MachineBasicBlock &T<br>
bool<br>
ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,<br>
MachineBasicBlock &FMBB) const {<br>
- // Reduce false anti-dependencies to let Swift's out-of-order execution<br>
+ // Reduce false anti-dependencies to let the target's out-of-order execution<br>
// engine do its thing.<br>
- return Subtarget.isSwift();<br>
+ return Subtarget.isProfitableToUnpredicate();<br>
}<br>
<br>
/// getInstrPredicate - If instruction is predicated, returns its predicate<br>
@@ -4178,7 +4178,7 @@ ARMBaseInstrInfo::getExecutionDomain(con<br>
<br>
// CortexA9 is particularly picky about mixing the two and wants these<br>
// converted.<br>
- if (Subtarget.isCortexA9() && !isPredicated(*MI) &&<br>
+ if (Subtarget.useNEONForFPMovs() && !isPredicated(*MI) &&<br>
(MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||<br>
MI->getOpcode() == ARM::VMOVS))<br>
return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=273544&r1=273543&r2=273544&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=273544&r1=273543&r2=273544&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 23 02:47:35 2016<br>
@@ -3024,7 +3024,8 @@ static SDValue LowerATOMIC_FENCE(SDValue<br>
if (Subtarget->isMClass()) {<br>
// Only a full system barrier exists in the M-class architectures.<br>
Domain = ARM_MB::SY;<br>
- } else if (Subtarget->isSwift() && Ord == AtomicOrdering::Release) {<br>
+ } else if (Subtarget->preferISHSTBarriers() &&<br>
+ Ord == AtomicOrdering::Release) {<br>
// Swift happens to implement ISHST barriers in a way that's compatible with<br>
// Release semantics but weaker than ISH so we'd be fools not to use<br>
// it. Beware: other processors probably don't!<br>
@@ -12236,7 +12237,7 @@ Instruction* ARMTargetLowering::emitLead<br>
/*FALLTHROUGH*/<br>
case AtomicOrdering::Release:<br>
case AtomicOrdering::AcquireRelease:<br>
- if (Subtarget->isSwift())<br>
+ if (Subtarget->preferISHSTBarriers())<br>
return makeDMB(Builder, ARM_MB::ISHST);<br>
// FIXME: add a comment with a link to documentation justifying this.<br>
else<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=273544&r1=273543&r2=273544&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=273544&r1=273543&r2=273544&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jun 23 02:47:35 2016<br>
@@ -321,19 +321,16 @@ def DontUseFusedMAC : Predicate<"!(TM.O<br>
" Subtarget->hasVFP4()) || "<br>
"Subtarget->isTargetDarwin()">;<br>
<br>
-// VGETLNi32 is microcoded on Swift - prefer VMOV.<br>
-def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;<br>
-def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;<br>
+def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">;<br>
+def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">;<br>
<br>
-// VDUP.32 is microcoded on Swift - prefer VMOV.<br>
-def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;<br>
-def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;<br>
+def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">;<br>
+def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">;<br>
<br>
-// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as<br>
-// this allows more effective execution domain optimization. See<br>
-// setExecutionDomain().<br>
-def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;<br>
-def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;<br>
+def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"<br>
+ "!Subtarget->useNEONForSinglePrecisionFP()">;<br>
+def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"<br>
+ "Subtarget->useNEONForSinglePrecisionFP()">;<br>
<br>
def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;<br>
def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=273544&r1=273543&r2=273544&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=273544&r1=273543&r2=273544&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jun 23 02:47:35 2016<br>
@@ -154,6 +154,12 @@ void ARMSubtarget::initializeEnvironment<br>
HasCRC = false;<br>
HasRAS = false;<br>
HasZeroCycleZeroing = false;<br>
+ IsProfitableToUnpredicate = false;<br>
+ HasSlowVGETLNi32 = false;<br>
+ HasSlowVDUP32 = false;<br>
+ PreferVMOVSR = false;<br>
+ PreferISHST = false;<br>
+ UseNEONForFPMovs = false;<br>
StrictAlign = false;<br>
HasDSP = false;<br>
UseNaClTrap = false;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=273544&r1=273543&r2=273544&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=273544&r1=273543&r2=273544&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 23 02:47:35 2016<br>
@@ -218,6 +218,24 @@ protected:<br>
/// particularly effective at zeroing a VFP register.<br>
bool HasZeroCycleZeroing;<br>
<br>
+ /// If true, if conversion may decide to leave some instructions unpredicated.<br>
+ bool IsProfitableToUnpredicate;<br>
+<br>
+ /// If true, VMOV will be favored over VGETLNi32.<br>
+ bool HasSlowVGETLNi32;<br>
+<br>
+ /// If true, VMOV will be favored over VDUP.<br>
+ bool HasSlowVDUP32;<br>
+<br>
+ /// If true, VMOVSR will be favored over VMOVDRR.<br>
+ bool PreferVMOVSR;<br>
+<br>
+ /// If true, ISHST barriers will be used for Release semantics.<br>
+ bool PreferISHST;<br>
+<br>
+ /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.<br>
+ bool UseNEONForFPMovs;<br>
+<br>
/// StrictAlign - If true, the subtarget disallows unaligned memory<br>
/// accesses for some types. For details, see<br>
/// ARMTargetLowering::allowsMisalignedMemoryAccesses().<br>
@@ -376,6 +394,12 @@ public:<br>
bool hasTrustZone() const { return HasTrustZone; }<br>
bool has8MSecExt() const { return Has8MSecExt; }<br>
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }<br>
+ bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }<br>
+ bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }<br>
+ bool hasSlowVDUP32() const { return HasSlowVDUP32; }<br>
+ bool preferVMOVSR() const { return PreferVMOVSR; }<br>
+ bool preferISHSTBarriers() const { return PreferISHST; }<br>
+ bool useNEONForFPMovs() const { return UseNEONForFPMovs; }<br>
bool prefers32BitThumb() const { return Pref32BitThumb; }<br>
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }<br>
bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }<br>
<br>
<br>
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</blockquote></div><div dir="ltr">-- <br></div><div data-smartmail="gmail_signature">Mike<br>Sent from phone</div>