[PATCH] D21560: Relax the clearance calculating for breaking partial register dependency.

[Joerg Sonnenberger via llvm-commits]

On Tue, Jun 21, 2016 at 07:16:14PM +0200, Joerg Sonnenberger via llvm-commits wrote:
> On Tue, Jun 21, 2016 at 05:04:11PM +0000, Dehao Chen via llvm-commits wrote:
> > LLVM assumes that large clearance will hide the partial register spill
> > penalty. But in our experiment, 16 clearance is too small. As the
> > inserted XOR is normally fairly cheap, we should have a higher
> > clearance threshold to aggressively insert XORs that is necessary to
> > break partial register dependency.
> 
> What's the code size impact here?

As discussed on IRC, what I am missing here are some numbers, ideally
for some (public) (well-known) benchmarks to illustrate the impact of
the setting for code size and performance with more than two data points
(16 vs 64). Otherwise the next person to look at it has no chance to
understand and falsify the choice.

Joerg