[PATCH] D21560: Relax the clearance calculating for breaking partial register dependency.

[Dehao Chen via llvm-commits]

danielcdh created this revision.
danielcdh added reviewers: mkuper, davidxl, wmi.
danielcdh added a subscriber: llvm-commits.

LLVM assumes that large clearance will hide the partial register spill penalty. But in our experiment, 16 clearance is too small. As the inserted XOR is normally fairly cheap, we should have a higher clearance threshold to aggressively insert XORs that is necessary to break partial register dependency.

http://reviews.llvm.org/D21560

Files:
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/vec_int_to_fp.ll

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