[llvm] r273244 - Replace silly uses of 'signed' with 'int'
David Majnemer via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 20 22:29:50 PDT 2016
On Mon, Jun 20, 2016 at 10:19 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> Was the change to StringRef.h supposed to be part of this?
>
llvm::ConstantFoldLoadFromConstPtr had a poor use of 'signed' which I chose
to fix by make it a little easier to iterate over StringRefs.
I can see arguments for adding the 'bytes' range accessor in a different
commit though.
>
> On Mon, Jun 20, 2016 at 10:10 PM, David Majnemer via llvm-commits <
> llvm-commits at lists.llvm.org> wrote:
>
>> Author: majnemer
>> Date: Tue Jun 21 00:10:24 2016
>> New Revision: 273244
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=273244&view=rev
>> Log:
>> Replace silly uses of 'signed' with 'int'
>>
>> Modified:
>> llvm/trunk/include/llvm/ADT/StringRef.h
>> llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h
>> llvm/trunk/lib/Analysis/ConstantFolding.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>> llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
>> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>> llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
>> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
>> llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>>
>> Modified: llvm/trunk/include/llvm/ADT/StringRef.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/ADT/StringRef.h (original)
>> +++ llvm/trunk/include/llvm/ADT/StringRef.h Tue Jun 21 00:10:24 2016
>> @@ -10,6 +10,7 @@
>> #ifndef LLVM_ADT_STRINGREF_H
>> #define LLVM_ADT_STRINGREF_H
>>
>> +#include "llvm/ADT/iterator_range.h"
>> #include "llvm/Support/Compiler.h"
>> #include <algorithm>
>> #include <cassert>
>> @@ -101,6 +102,9 @@ namespace llvm {
>> const unsigned char *bytes_end() const {
>> return reinterpret_cast<const unsigned char *>(end());
>> }
>> + iterator_range<const unsigned char *> bytes() const {
>> + return make_range(bytes_begin(), bytes_end());
>> + }
>>
>> /// @}
>> /// @name String Operations
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h Tue Jun 21
>> 00:10:24 2016
>> @@ -72,7 +72,7 @@ namespace llvm {
>>
>> /// Heuristics for estimating register pressure.
>> unsigned ParallelLiveRanges;
>> - signed HorizontalVerticalBalance;
>> + int HorizontalVerticalBalance;
>>
>> public:
>> ResourcePriorityQueue(SelectionDAGISel *IS);
>> @@ -103,14 +103,14 @@ namespace llvm {
>>
>> /// Single cost function reflecting benefit of scheduling SU
>> /// in the current cycle.
>> - signed SUSchedulingCost (SUnit *SU);
>> + int SUSchedulingCost (SUnit *SU);
>>
>> /// InitNumRegDefsLeft - Determine the # of regs defined by this
>> node.
>> ///
>> void initNumRegDefsLeft(SUnit *SU);
>> void updateNumRegDefsLeft(SUnit *SU);
>> - signed regPressureDelta(SUnit *SU, bool RawPressure = false);
>> - signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
>> + int regPressureDelta(SUnit *SU, bool RawPressure = false);
>> + int rawRegPressureDelta (SUnit *SU, unsigned RCId);
>>
>> bool empty() const override { return Queue.empty(); }
>>
>>
>> Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
>> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jun 21 00:10:24 2016
>> @@ -17,6 +17,7 @@
>>
>> //===----------------------------------------------------------------------===//
>>
>> #include "llvm/Analysis/ConstantFolding.h"
>> +#include "llvm/ADT/STLExtras.h"
>> #include "llvm/ADT/SmallPtrSet.h"
>> #include "llvm/ADT/SmallVector.h"
>> #include "llvm/ADT/StringMap.h"
>> @@ -564,7 +565,7 @@ Constant *llvm::ConstantFoldLoadFromCons
>> // directly if string length is small enough.
>> StringRef Str;
>> if (getConstantStringInfo(CE, Str) && !Str.empty()) {
>> - unsigned StrLen = Str.size();
>> + size_t StrLen = Str.size();
>> unsigned NumBits = Ty->getPrimitiveSizeInBits();
>> // Replace load with immediate integer if the result is an integer
>> or fp
>> // value.
>> @@ -573,15 +574,13 @@ Constant *llvm::ConstantFoldLoadFromCons
>> APInt StrVal(NumBits, 0);
>> APInt SingleChar(NumBits, 0);
>> if (DL.isLittleEndian()) {
>> - for (signed i = StrLen-1; i >= 0; i--) {
>> - SingleChar = (uint64_t) Str[i] &
>> - std::numeric_limits<unsigned char>::max();
>> + for (unsigned char C : reverse(Str.bytes())) {
>> + SingleChar = static_cast<uint64_t>(C);
>> StrVal = (StrVal << 8) | SingleChar;
>> }
>> } else {
>> - for (unsigned i = 0; i < StrLen; i++) {
>> - SingleChar = (uint64_t) Str[i] &
>> - std::numeric_limits<unsigned char>::max();
>> + for (unsigned char C : Str.bytes()) {
>> + SingleChar = static_cast<uint64_t>(C);
>> StrVal = (StrVal << 8) | SingleChar;
>> }
>> // Append NULL at the end.
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jun 21
>> 00:10:24 2016
>> @@ -4692,7 +4692,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N)
>> TruncVT = EVT::getVectorVT(Ctx, TruncVT,
>> VT.getVectorNumElements());
>>
>> // Determine the residual right-shift amount.
>> - signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
>> + int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
>>
>> // If the shift is not a no-op (in which case this should be just
>> a sign
>> // extend already), the truncated to type is legal, sign_extend is
>> legal
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp Tue Jun
>> 21 00:10:24 2016
>> @@ -37,7 +37,7 @@ static cl::opt<bool> DisableDFASched("di
>> cl::ZeroOrMore, cl::init(false),
>> cl::desc("Disable use of DFA during scheduling"));
>>
>> -static cl::opt<signed> RegPressureThreshold(
>> +static cl::opt<int> RegPressureThreshold(
>> "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore,
>> cl::init(5),
>> cl::desc("Track reg pressure and switch priority to in-depth"));
>>
>> @@ -323,8 +323,8 @@ void ResourcePriorityQueue::reserveResou
>> }
>> }
>>
>> -signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned
>> RCId) {
>> - signed RegBalance = 0;
>> +int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId)
>> {
>> + int RegBalance = 0;
>>
>> if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
>> return RegBalance;
>> @@ -357,8 +357,8 @@ signed ResourcePriorityQueue::rawRegPres
>> /// The RawPressure flag makes this function to ignore
>> /// existing reg file sizes, and report raw def/use
>> /// balance.
>> -signed ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool
>> RawPressure) {
>> - signed RegBalance = 0;
>> +int ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure)
>> {
>> + int RegBalance = 0;
>>
>> if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
>> return RegBalance;
>> @@ -398,9 +398,9 @@ static const unsigned FactorOne = 2;
>>
>> /// Returns single number reflecting benefit of scheduling SU
>> /// in the current cycle.
>> -signed ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
>> +int ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
>> // Initial trivial priority.
>> - signed ResCount = 1;
>> + int ResCount = 1;
>>
>> // Do not waste time on a node that is already scheduled.
>> if (SU->isScheduled)
>> @@ -601,7 +601,7 @@ SUnit *ResourcePriorityQueue::pop() {
>>
>> std::vector<SUnit *>::iterator Best = Queue.begin();
>> if (!DisableDFASched) {
>> - signed BestCost = SUSchedulingCost(*Best);
>> + int BestCost = SUSchedulingCost(*Best);
>> for (std::vector<SUnit *>::iterator I = std::next(Queue.begin()),
>> E = Queue.end(); I != E; ++I) {
>>
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Jun 21
>> 00:10:24 2016
>> @@ -9475,14 +9475,13 @@ bool checkValueWidth(SDValue V, unsigned
>> // isEquivalentMaskless() is the code for testing if the AND can be
>> removed
>> // factored out of the DAG recognition as the DAG can take several forms.
>>
>> -static
>> -bool isEquivalentMaskless(unsigned CC, unsigned width,
>> - ISD::LoadExtType ExtType, signed AddConstant,
>> - signed CompConstant) {
>> +static bool isEquivalentMaskless(unsigned CC, unsigned width,
>> + ISD::LoadExtType ExtType, int
>> AddConstant,
>> + int CompConstant) {
>> // By being careful about our equations and only writing the in term
>> // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
>> // make them generally applicable to all bit widths.
>> - signed MaxUInt = (1 << width);
>> + int MaxUInt = (1 << width);
>>
>> // For the purposes of these comparisons sign extending the type is
>> // equivalent to zero extending the add and displacing it by half the
>> integer
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Jun 21 00:10:24 2016
>> @@ -931,7 +931,7 @@ void ARMFastISel::AddLoadStoreOperands(M
>> // ARM halfword load/stores and signed byte loads need an additional
>> // operand.
>> if (useAM3) {
>> - signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) :
>> Addr.Offset;
>> + int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
>> MIB.addReg(0);
>> MIB.addImm(Imm);
>> } else {
>> @@ -945,7 +945,7 @@ void ARMFastISel::AddLoadStoreOperands(M
>> // ARM halfword load/stores and signed byte loads need an additional
>> // operand.
>> if (useAM3) {
>> - signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) :
>> Addr.Offset;
>> + int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
>> MIB.addReg(0);
>> MIB.addImm(Imm);
>> } else {
>>
>> Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Tue Jun
>> 21 00:10:24 2016
>> @@ -1797,15 +1797,13 @@ int HexagonAsmParser::processInstruction
>> MCOperand &MO = Inst.getOperand(1);
>> int64_t Value;
>> if (MO.getExpr()->evaluateAsAbsolute(Value)) {
>> - unsigned long long u64 = Value;
>> - signed int s8 = (u64 >> 32) & 0xFFFFFFFF;
>> - if (s8 < -128 || s8 > 127)
>> + int s8 = Hi_32(Value);
>> + if (!isInt<8>(s8))
>> OutOfRange(IDLoc, s8, -128);
>> MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
>> MCConstantExpr::create(s8, Context), Context))); // upper 32
>> auto Expr = HexagonMCExpr::create(
>> - MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),
>> - Context);
>> + MCConstantExpr::create(Lo_32(Value), Context), Context);
>> HexagonMCInstrInfo::setMustExtend(*Expr,
>> HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
>> MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
>> Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
>>
>> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Tue
>> Jun 21 00:10:24 2016
>> @@ -416,12 +416,12 @@ public:
>> uint32_t Offset = Fixup.getOffset();
>> unsigned NumBytes = getFixupKindNumBytes(Kind);
>> assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
>> - char* InstAddr = Data + Offset;
>> + char *InstAddr = Data + Offset;
>>
>> Value = adjustFixupValue(Kind, FixupValue);
>> if(!Value)
>> return;
>> - signed sValue = (signed)Value;
>> + int sValue = (int)Value;
>>
>> switch((unsigned)Kind) {
>> default:
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp Tue Jun 21
>> 00:10:24 2016
>> @@ -516,7 +516,7 @@ void MipsSEFrameLowering::emitPrologue(M
>> unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
>> assert(isInt<16>(MFI->getMaxAlignment()) &&
>> "Function's alignment size requirement is not supported.");
>> - int MaxAlign = - (signed) MFI->getMaxAlignment();
>> + int MaxAlign = -(int)MFI->getMaxAlignment();
>>
>> BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO)
>> .addImm(MaxAlign);
>> BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Jun 21 00:10:24 2016
>> @@ -262,7 +262,7 @@ def HI16 : SDNodeXForm<imm, [{
>>
>> def HA16 : SDNodeXForm<imm, [{
>> // Transformation function: shift the immediate value down into the
>> low bits.
>> - signed int Val = N->getZExtValue();
>> + int Val = N->getZExtValue();
>> return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
>> }]>;
>> def MB : SDNodeXForm<imm, [{
>>
>> Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=273244&r1=273243&r2=273244&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>> (original)
>> +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue
>> Jun 21 00:10:24 2016
>> @@ -1398,7 +1398,7 @@ Instruction *InstCombiner::visitGetEleme
>> if (Op1 == &GEP)
>> return nullptr;
>>
>> - signed DI = -1;
>> + int DI = -1;
>>
>> for (auto I = PN->op_begin()+1, E = PN->op_end(); I !=E; ++I) {
>> GetElementPtrInst *Op2 = dyn_cast<GetElementPtrInst>(*I);
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>
>
>
>
> --
> ~Craig
>
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