<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 20, 2016 at 10:19 PM, Craig Topper <span dir="ltr"><<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div dir="ltr">Was the change to StringRef.h supposed to be part of this?</div></blockquote><div><br></div><div>llvm::ConstantFoldLoadFromConstPtr had a poor use of 'signed' which I chose to fix by make it a little easier to iterate over StringRefs.<br></div><div><br></div><div>I can see arguments for adding the 'bytes' range accessor in a different commit though.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex"><div class="gmail_extra"><div><div class="h5"><br><div class="gmail_quote">On Mon, Jun 20, 2016 at 10:10 PM, David Majnemer via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">Author: majnemer<br>
Date: Tue Jun 21 00:10:24 2016<br>
New Revision: 273244<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=273244&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=273244&view=rev</a><br>
Log:<br>
Replace silly uses of 'signed' with 'int'<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/ADT/StringRef.h<br>
llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h<br>
llvm/trunk/lib/Analysis/ConstantFolding.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp<br>
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp<br>
llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td<br>
llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/ADT/StringRef.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/ADT/StringRef.h (original)<br>
+++ llvm/trunk/include/llvm/ADT/StringRef.h Tue Jun 21 00:10:24 2016<br>
@@ -10,6 +10,7 @@<br>
#ifndef LLVM_ADT_STRINGREF_H<br>
#define LLVM_ADT_STRINGREF_H<br>
<br>
+#include "llvm/ADT/iterator_range.h"<br>
#include "llvm/Support/Compiler.h"<br>
#include <algorithm><br>
#include <cassert><br>
@@ -101,6 +102,9 @@ namespace llvm {<br>
const unsigned char *bytes_end() const {<br>
return reinterpret_cast<const unsigned char *>(end());<br>
}<br>
+ iterator_range<const unsigned char *> bytes() const {<br>
+ return make_range(bytes_begin(), bytes_end());<br>
+ }<br>
<br>
/// @}<br>
/// @name String Operations<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/ResourcePriorityQueue.h Tue Jun 21 00:10:24 2016<br>
@@ -72,7 +72,7 @@ namespace llvm {<br>
<br>
/// Heuristics for estimating register pressure.<br>
unsigned ParallelLiveRanges;<br>
- signed HorizontalVerticalBalance;<br>
+ int HorizontalVerticalBalance;<br>
<br>
public:<br>
ResourcePriorityQueue(SelectionDAGISel *IS);<br>
@@ -103,14 +103,14 @@ namespace llvm {<br>
<br>
/// Single cost function reflecting benefit of scheduling SU<br>
/// in the current cycle.<br>
- signed SUSchedulingCost (SUnit *SU);<br>
+ int SUSchedulingCost (SUnit *SU);<br>
<br>
/// InitNumRegDefsLeft - Determine the # of regs defined by this node.<br>
///<br>
void initNumRegDefsLeft(SUnit *SU);<br>
void updateNumRegDefsLeft(SUnit *SU);<br>
- signed regPressureDelta(SUnit *SU, bool RawPressure = false);<br>
- signed rawRegPressureDelta (SUnit *SU, unsigned RCId);<br>
+ int regPressureDelta(SUnit *SU, bool RawPressure = false);<br>
+ int rawRegPressureDelta (SUnit *SU, unsigned RCId);<br>
<br>
bool empty() const override { return Queue.empty(); }<br>
<br>
<br>
Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jun 21 00:10:24 2016<br>
@@ -17,6 +17,7 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
#include "llvm/Analysis/ConstantFolding.h"<br>
+#include "llvm/ADT/STLExtras.h"<br>
#include "llvm/ADT/SmallPtrSet.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
#include "llvm/ADT/StringMap.h"<br>
@@ -564,7 +565,7 @@ Constant *llvm::ConstantFoldLoadFromCons<br>
// directly if string length is small enough.<br>
StringRef Str;<br>
if (getConstantStringInfo(CE, Str) && !Str.empty()) {<br>
- unsigned StrLen = Str.size();<br>
+ size_t StrLen = Str.size();<br>
unsigned NumBits = Ty->getPrimitiveSizeInBits();<br>
// Replace load with immediate integer if the result is an integer or fp<br>
// value.<br>
@@ -573,15 +574,13 @@ Constant *llvm::ConstantFoldLoadFromCons<br>
APInt StrVal(NumBits, 0);<br>
APInt SingleChar(NumBits, 0);<br>
if (DL.isLittleEndian()) {<br>
- for (signed i = StrLen-1; i >= 0; i--) {<br>
- SingleChar = (uint64_t) Str[i] &<br>
- std::numeric_limits<unsigned char>::max();<br>
+ for (unsigned char C : reverse(Str.bytes())) {<br>
+ SingleChar = static_cast<uint64_t>(C);<br>
StrVal = (StrVal << 8) | SingleChar;<br>
}<br>
} else {<br>
- for (unsigned i = 0; i < StrLen; i++) {<br>
- SingleChar = (uint64_t) Str[i] &<br>
- std::numeric_limits<unsigned char>::max();<br>
+ for (unsigned char C : Str.bytes()) {<br>
+ SingleChar = static_cast<uint64_t>(C);<br>
StrVal = (StrVal << 8) | SingleChar;<br>
}<br>
// Append NULL at the end.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jun 21 00:10:24 2016<br>
@@ -4692,7 +4692,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N)<br>
TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());<br>
<br>
// Determine the residual right-shift amount.<br>
- signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();<br>
+ int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();<br>
<br>
// If the shift is not a no-op (in which case this should be just a sign<br>
// extend already), the truncated to type is legal, sign_extend is legal<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp Tue Jun 21 00:10:24 2016<br>
@@ -37,7 +37,7 @@ static cl::opt<bool> DisableDFASched("di<br>
cl::ZeroOrMore, cl::init(false),<br>
cl::desc("Disable use of DFA during scheduling"));<br>
<br>
-static cl::opt<signed> RegPressureThreshold(<br>
+static cl::opt<int> RegPressureThreshold(<br>
"dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5),<br>
cl::desc("Track reg pressure and switch priority to in-depth"));<br>
<br>
@@ -323,8 +323,8 @@ void ResourcePriorityQueue::reserveResou<br>
}<br>
}<br>
<br>
-signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {<br>
- signed RegBalance = 0;<br>
+int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {<br>
+ int RegBalance = 0;<br>
<br>
if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())<br>
return RegBalance;<br>
@@ -357,8 +357,8 @@ signed ResourcePriorityQueue::rawRegPres<br>
/// The RawPressure flag makes this function to ignore<br>
/// existing reg file sizes, and report raw def/use<br>
/// balance.<br>
-signed ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {<br>
- signed RegBalance = 0;<br>
+int ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {<br>
+ int RegBalance = 0;<br>
<br>
if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())<br>
return RegBalance;<br>
@@ -398,9 +398,9 @@ static const unsigned FactorOne = 2;<br>
<br>
/// Returns single number reflecting benefit of scheduling SU<br>
/// in the current cycle.<br>
-signed ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {<br>
+int ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {<br>
// Initial trivial priority.<br>
- signed ResCount = 1;<br>
+ int ResCount = 1;<br>
<br>
// Do not waste time on a node that is already scheduled.<br>
if (SU->isScheduled)<br>
@@ -601,7 +601,7 @@ SUnit *ResourcePriorityQueue::pop() {<br>
<br>
std::vector<SUnit *>::iterator Best = Queue.begin();<br>
if (!DisableDFASched) {<br>
- signed BestCost = SUSchedulingCost(*Best);<br>
+ int BestCost = SUSchedulingCost(*Best);<br>
for (std::vector<SUnit *>::iterator I = std::next(Queue.begin()),<br>
E = Queue.end(); I != E; ++I) {<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Jun 21 00:10:24 2016<br>
@@ -9475,14 +9475,13 @@ bool checkValueWidth(SDValue V, unsigned<br>
// isEquivalentMaskless() is the code for testing if the AND can be removed<br>
// factored out of the DAG recognition as the DAG can take several forms.<br>
<br>
-static<br>
-bool isEquivalentMaskless(unsigned CC, unsigned width,<br>
- ISD::LoadExtType ExtType, signed AddConstant,<br>
- signed CompConstant) {<br>
+static bool isEquivalentMaskless(unsigned CC, unsigned width,<br>
+ ISD::LoadExtType ExtType, int AddConstant,<br>
+ int CompConstant) {<br>
// By being careful about our equations and only writing the in term<br>
// symbolic values and well known constants (0, 1, -1, MaxUInt) we can<br>
// make them generally applicable to all bit widths.<br>
- signed MaxUInt = (1 << width);<br>
+ int MaxUInt = (1 << width);<br>
<br>
// For the purposes of these comparisons sign extending the type is<br>
// equivalent to zero extending the add and displacing it by half the integer<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Jun 21 00:10:24 2016<br>
@@ -931,7 +931,7 @@ void ARMFastISel::AddLoadStoreOperands(M<br>
// ARM halfword load/stores and signed byte loads need an additional<br>
// operand.<br>
if (useAM3) {<br>
- signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;<br>
+ int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;<br>
MIB.addReg(0);<br>
MIB.addImm(Imm);<br>
} else {<br>
@@ -945,7 +945,7 @@ void ARMFastISel::AddLoadStoreOperands(M<br>
// ARM halfword load/stores and signed byte loads need an additional<br>
// operand.<br>
if (useAM3) {<br>
- signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;<br>
+ int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;<br>
MIB.addReg(0);<br>
MIB.addImm(Imm);<br>
} else {<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Tue Jun 21 00:10:24 2016<br>
@@ -1797,15 +1797,13 @@ int HexagonAsmParser::processInstruction<br>
MCOperand &MO = Inst.getOperand(1);<br>
int64_t Value;<br>
if (MO.getExpr()->evaluateAsAbsolute(Value)) {<br>
- unsigned long long u64 = Value;<br>
- signed int s8 = (u64 >> 32) & 0xFFFFFFFF;<br>
- if (s8 < -128 || s8 > 127)<br>
+ int s8 = Hi_32(Value);<br>
+ if (!isInt<8>(s8))<br>
OutOfRange(IDLoc, s8, -128);<br>
MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(<br>
MCConstantExpr::create(s8, Context), Context))); // upper 32<br>
auto Expr = HexagonMCExpr::create(<br>
- MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),<br>
- Context);<br>
+ MCConstantExpr::create(Lo_32(Value), Context), Context);<br>
HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));<br>
MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32<br>
Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Tue Jun 21 00:10:24 2016<br>
@@ -416,12 +416,12 @@ public:<br>
uint32_t Offset = Fixup.getOffset();<br>
unsigned NumBytes = getFixupKindNumBytes(Kind);<br>
assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");<br>
- char* InstAddr = Data + Offset;<br>
+ char *InstAddr = Data + Offset;<br>
<br>
Value = adjustFixupValue(Kind, FixupValue);<br>
if(!Value)<br>
return;<br>
- signed sValue = (signed)Value;<br>
+ int sValue = (int)Value;<br>
<br>
switch((unsigned)Kind) {<br>
default:<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp Tue Jun 21 00:10:24 2016<br>
@@ -516,7 +516,7 @@ void MipsSEFrameLowering::emitPrologue(M<br>
unsigned VR = MF.getRegInfo().createVirtualRegister(RC);<br>
assert(isInt<16>(MFI->getMaxAlignment()) &&<br>
"Function's alignment size requirement is not supported.");<br>
- int MaxAlign = - (signed) MFI->getMaxAlignment();<br>
+ int MaxAlign = -(int)MFI->getMaxAlignment();<br>
<br>
BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);<br>
BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Jun 21 00:10:24 2016<br>
@@ -262,7 +262,7 @@ def HI16 : SDNodeXForm<imm, [{<br>
<br>
def HA16 : SDNodeXForm<imm, [{<br>
// Transformation function: shift the immediate value down into the low bits.<br>
- signed int Val = N->getZExtValue();<br>
+ int Val = N->getZExtValue();<br>
return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));<br>
}]>;<br>
def MB : SDNodeXForm<imm, [{<br>
<br>
Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=273244&r1=273243&r2=273244&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=273244&r1=273243&r2=273244&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue Jun 21 00:10:24 2016<br>
@@ -1398,7 +1398,7 @@ Instruction *InstCombiner::visitGetEleme<br>
if (Op1 == &GEP)<br>
return nullptr;<br>
<br>
- signed DI = -1;<br>
+ int DI = -1;<br>
<br>
for (auto I = PN->op_begin()+1, E = PN->op_end(); I !=E; ++I) {<br>
GetElementPtrInst *Op2 = dyn_cast<GetElementPtrInst>(*I);<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div></div></div><span class=""><font color="#888888">-- <br><div data-smartmail="gmail_signature">~Craig</div>
</font></span></div>
</blockquote></div><br></div></div>