[PATCH] D21540: AMDGPU: Define a schedule class for COPY.

[Matthias Braun via llvm-commits]

MatzeB added inline comments.

================
Comment at: lib/Target/AMDGPU/SISchedule.td:108
@@ -107,1 +107,3 @@
 
+def : InstRW<[WriteSALU], (instrs COPY)>;
+
----------------
arsenm wrote:
> copy should be either WriteSALU or WriteVALU, but both of these seem to just use SALU. Is there a way to change this depending on the instance of the instruction?
Yes, with `SchedWriteVariant`. take a look at lib/Target/AArch64/AArch64SchedCyclone.td for an example.


Repository:
  rL LLVM

http://reviews.llvm.org/D21540