[PATCH] D21540: AMDGPU: Define a schedule class for COPY.

[Matthias Braun via llvm-commits]

MatzeB created this revision.
MatzeB added reviewers: tstellarAMD, arsenm.
MatzeB added a subscriber: llvm-commits.
MatzeB set the repository for this revision to rL LLVM.
Herald added subscribers: kzhuravl, mcrosier, arsenm.

Proof of concept patch. I found this while analyzing some of the regressions in http://reviews.llvm.org/D19401 which are fixed by this, but the change should be good in general.

No testcase updates included here yet.

Repository:
  rL LLVM

http://reviews.llvm.org/D21540

Files:
  lib/Target/AMDGPU/SISchedule.td

Index: lib/Target/AMDGPU/SISchedule.td
===================================================================
--- lib/Target/AMDGPU/SISchedule.td
+++ lib/Target/AMDGPU/SISchedule.td
@@ -105,6 +105,8 @@
 def : HWVALUWriteRes<WriteDouble,     4>;
 def : HWVALUWriteRes<WriteDoubleAdd,  2>;
 
+def : InstRW<[WriteSALU], (instrs COPY)>;
+
 } // End SchedModel = SIFullSpeedModel
 
 let SchedModel = SIQuarterSpeedModel in {
@@ -115,4 +117,6 @@
 def : HWVALUWriteRes<WriteDouble,   16>;
 def : HWVALUWriteRes<WriteDoubleAdd, 8>;
 
+def : InstRW<[WriteSALU], (instrs COPY)>;
+
 }  // End SchedModel = SIQuarterSpeedModel


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